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參數資料
| 型號： | HMP8191 |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Encoder |
| 中文描述： | NTSC / PAL視頻編碼器 |
| 文件頁數： | 19/32頁 |
| 文件大小： | 227K |
| 代理商： | HMP8191 |
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19
TABLE 30. CRC_20 REGISTER
SUB ADDRESS = 18
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Reserved
00
B
5-0
Line 20
WSS CRC Data
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
111111
B
TABLE 31. CRC_283 REGISTER
SUB ADDRESS = 19
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Reserved
00
B
5-0
Line 283
WSS CRC Data
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
111111
B
TABLE 32. START H_BLANK LOW REGISTER
SUB ADDRESS = 20
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
LSB Assert BLANK
Output Signal
(Horizontal)
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
H
. This reg-
ister is ignored unless BLANK is configured as an output.
4A
H
TABLE 33. START H_BLANK HIGH REGISTER
SUB ADDRESS = 21
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-2
Reserved
000000
B
1-0
MSB Assert BLANK
Output Signal
(Horizontal)
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
H
. This reg-
ister is ignored unless BLANK is configured as an output.
11
B
TABLE 34. END H_BLANK REGISTER
SUB ADDRESS = 22
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
(Horizontal)
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000
H
. This register is ignored
unless BLANK is configured as an output.
7A
H
HMP8190, HMP8191
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