- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385388 > HMP8191 (Intersil Corporation) NTSC/PAL Video Encoder PDF資料下載
參數(shù)資料
| 型號： | HMP8191 |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Encoder |
| 中文描述： | NTSC / PAL視頻編碼器 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 227K |
| 代理商： | HMP8191 |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
4
8-Bit YCbCr Format
When 8-bit YCbCr format is selected, the data is latched on
each rising edge of CLK2. The pixel data must be [Cb Y Cr
Y’ Cb Y Cr Y’ . . . ], with the first active data each scan line
being Cb data. The pixel input timing is shown in Figure 1.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency.
16-Bit YCbCr Format
When 16-bit YCbCr format is selected, the pixel data is
latched on the rising edge of CLK2 while CLK is low. The
pixel input timing is shown in Figure 2.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In these modes of operation, CLK is
one-half the CLK2 frequency.
8-Bit BT.656 Format
When BT.656 format is selected, data is latched on each
rising edge of CLK2. The pixel input timing is shown in
Figure 3. The figure shows the EAV code at the end of the
line. The format of the SAV and EAV codes are shown in
Table 3.
The BT.656 input may also include ancillary data to load the
VBI or RTCI data registers. The HMP8190/HMP8191 will
use the ancillary data when enabled in the VBI data input
and timing I/O registers. The ancillary data formats and the
enable registers are described later in this datasheet.
As inputs, the BLANK, HSYNC, and VSYNC pins are
ignored since all timing is derived from the EAV and SAV
sequences within the data stream. As outputs, BLANK,
HSYNC and VSYNC are output following the rising edge of
CLK2. If the CLK pin is configured as an input, it is ignored. If
configured as an output, it is one-half the CLK2 frequency.
FIGURE 1. PIXEL INPUT TIMING - 8-BIT YCBCR
FIGURE 2. PIXEL INPUT TIMING - 16-BIT YCBCR
Cb 0
Y 0
Cr 0
Y 1
Cb 2
Y 2
CLK2
P8-P15
BLANK
(INPUT)
Y N
BLANK
(OUTPUT)
Y 0
Y 1
Y 2
Y 3
Y 4
Y 5
CLK
P8-P15
BLANK
(INPUT)
Cb 0
Cr 0
Cb 2
Cr 2
Cb 4
Cr 4
P0-P7
CLK2
Y N
Cr N-1
BLANK
(OUTPUT)
HMP8190, HMP8191
相關PDF資料 |
PDF描述 |
|---|---|
| HMP8191CN | NTSC/PAL Video Encoder |
| HMPS650 | NPN SILICON TRANSISTOR |
| HMPSH10 | NPN EPITAXIAL PLANAR TRANSISTOR |
| HMS77C1000A | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| HMS77C1001A | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMP8191CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8201CN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Compression/Expansion Circuit |
| HMP820SGR32GM | 制造商:Advanced Micro Devices 功能描述:PHENOM II MOBILE X3 P820 25W S1G4 - Trays |
| HMP9701 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:AC’97 Audio Codec |
| HMP9701A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:AC’97 Audio Codec |
發(fā)布緊急采購，3分鐘左右您將得到回復。