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參數資料
| 型號： | HMP8191 |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Encoder |
| 中文描述： | NTSC / PAL視頻編碼器 |
| 文件頁數： | 20/32頁 |
| 文件大?。?/td> | 227K |
| 代理商： | HMP8191 |
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20
TABLE 35. START V_BLANK LOW REGISTER
SUB ADDRESS = 23
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
LSB Assert BLANK
Output Signal
(Vertical)
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
H
(note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is con-
figured as an output.
03
H
TABLE 36. START V_BLANK HIGH REGISTER
SUB ADDRESS = 24
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-1
Reserved
0000000
B
0
MSB Assert BLANK
Output Signal
(Vertical)
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register. This register is ignored unless BLANK is configured as an output.
1
B
TABLE 37. END V_BLANK REGISTER
SUB ADDRESS = 25
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
(Vertical)
During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel
input data (and what line number to start generating active output video) each odd field; for
even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
H
(note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is con-
figured as an output.
13
H
TABLE 38. FIELD CONTROL REGISTER 1
SUB ADDRESS = 26
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Field Detect
Window Size Low
This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect
Window Size value. The value specifies the number of 1x clock cycles in the detection window
before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge
of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the
FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured
as inputs.
80
H
TABLE 39. FIELD CONTROL REGISTER 2
SUB ADDRESS = 27
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-4
Half Line Count
Reset Value
These bits specify the value to load to the vertical half line counter when the selected edge of
VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.
00000
B
2
VSYNC Edge
Select
This bit specifies whetherthe encoder uses the leading or trailing edge ofVSYNC to determine
the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are config-
ured as inputs.
0 = leading edge
1 = trailing edge
0
B
HMP8190, HMP8191
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