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參數資料
| 型號： | HTVDS84 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance Microcontroller With Macro Instruction and Voice Synthesizer and Tone Generator(高性能、8位微控制器，帶宏指令、聲話音成器和聲音發生器) |
| 中文描述： | 8位高性能微控制器，帶有宏觀指導和語音合成器和音發生器（高性能，8位微控制器，帶宏指令，聲話音成器和聲音發生器） |
| 文件頁數： | 13/44頁 |
| 文件大小： | 275K |
| 代理商： | HTVDS84 |
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HTVDS84
13
June 7, 2000
Stack register
Stack
The stack register is a special part of the mem-
ory used to save the contents of the program
counter (PC). This stack is organized into two
levels. It is neither part of the data nor part of
the program space, and cannot be read or writ-
ten to. Its activated level is indexed by a stack
pointer (SP) and cannot be read or written to.
At a subroutine call or interrupt acknowledg-
ment, the contents of the program counter are
pushed onto the stack. The program counter is
restored to its previous value from the stack at
the end of a subroutine or interrupt routine,
which is signaled by a return instruction (RET
or RETI). After a chip resets, SP will point to
the top of the stack.
The interrupt request flag will be recorded but
the acknowledgment will be inhibited when the
stack is full and a non-masked interrupt takes
place. After the stack pointer is decremented
(by RET or RETI), the interrupt will be ser-
viced. This feature prevents stack overflow and
allows programmers to use the structure more
easily. In a similar case, if the stack is full and a
"CALL" is subsequently executed, stack over-
flow occurs and the first entry is lost.
Data memory
RAM
The data memory is designed with 103x 8 bits.
The data memory is further divided into two
functional groups; namely, special function reg-
istersandgeneralpurposedatamemory(80x8).
Although most of them can be read or be writ-
ten to, some are read only.
The special function registers include an indi-
rect addressing register (R0; 00H), memory
pointer register (MP0; 01H), accumulator
(ACC; 05H), program counter lower-order byte
register (PCL; 06H), table pointer (TBLP; 07H),
table higher-order byte register (TBLH; 08H),
status register (STATUS; 0AH), interrupt con-
trol register (INTC; 0BH), I/O registers (PA;
12H, PB; 14H) and I/O control registers (PAC;
13H, PBC; 15H), clock MUX register of sam-
pling rate register (TMRC; 1DH). The 20H to
2DH are used for sound and tone (melody) syn-
thesis. The function registers include a
lower-order byte register (PDAL; 20H, 24H) of
D/A data, higher-order byte register (PDAH;
21H, 25H) of D/A data, volume control register
(VOL; 22H, 26H), sampling rate control regis-
ter (SR; 23H, 27H), voice ROM data register
(CROM; 2CH) and control register (CROMC;
2DH).
R0
MP0
ACC
PCL
TBLP
TBLH
STATUS
INTC
PA
PAC
PB
PBC
TMRC
PDA1L
PDA1H
VOL1
SR1
PDA2L
PDA2H
VOL2
SR2
CROM
CROMC
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
11H
12H
13H
14H
15H
16H
1CH
1DH
1EH
1FH
General Purpose
Data Memory
*R/W
*R/W
*R/W
*R/W
*R/W
*R
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*R/W
*W
*R/W
20H
21H
22H
23H
24H
25H
26H
27H
28H
2BH
2CH
2DH
2EH
2FH
30H
7FH
Note: *R/W: readable/writable
*R: read only
*W: write only
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