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參數資料
| 型號： | HTVDS84 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance Microcontroller With Macro Instruction and Voice Synthesizer and Tone Generator(高性能、8位微控制器，帶宏指令、聲話音成器和聲音發生器) |
| 中文描述： | 8位高性能微控制器，帶有宏觀指導和語音合成器和音發生器（高性能，8位微控制器，帶宏指令，聲話音成器和聲音發生器） |
| 文件頁數： | 21/44頁 |
| 文件大小： | 275K |
| 代理商： | HTVDS84 |
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HTVDS84
21
June 7, 2000
The handshaking between the microcontroller
and voice ROM is through a ROM data register
(CROM. 2CH) and control register (CROMC;
2DH).
The voice ROM with two 20-bit address counter
decoder, writing address to the address counter
which are selected by bit1 of CROMC (0: coun-
ter 1 , 1: counter 2). Load the contents of the ad-
dress counter to the voice ROM cell for reading,
and that which contains the address counter
are selected by bit0 of CROMC (0: counter 1 , 1:
counter 2). The bit 7 to bit 2 of CROMC are not
valid.
The related voice ROM address has to be writ-
ten in the address counter first if the
microcontroller attempts to read the sound or
tone (melody) data in the voice ROM. After the
microcontroller finishes reading a byte of data,
its internal address counter will automatically
be incremented by one. In this case, reading
continuousdataonlyrequiresloadingthestart-
ing address to the CROM .
The lower-order nibble is valid whereas the
higher-order nibble is not valid in the CROM .
Based on this difference, the start address has
to be divided into six nibbles, and written into
the CROM six times. The lower-order nibble
and higher-order nibble data can then be read
back by reading twice after the sound or tone
(melody) starting address is written.
The reading of one byte of data must delay at
least twenty instruction cycles after the ad-
dress is exchanged however the address is pro-
grammed or automatically increase by one. For
example, if the starting address of the sound
data to be read is 0CF0H by address counter 1,
the program of reading one byte of sound or
tone (melody) data is as shown below:
; Selected #1 address counter
; Write the fourth nibble address
; Set reflashes to #1
MOV
A, 00H
; Set read to #1
MOV
CROM, A
MOV
A, 0011b
; Write the fifth and sixth addresses
MOV
CROMC, A
CLR
CROM
; Write the first nibble address
CLR
CROM
MOV
A, 00H
; Delay 20 instruction cycles
MOV
CROM, A
CALL
DELAY
; Write the second nibble address
MOV
A, 0FH
; Read the lower order nibble data
MOV
CROM, A
SWAPA
CROM
; Write the third nibble address
; Read the high-order nibble data
MOV
A, 0CH
OR
A, CROM
MOV
CROM, A
SWAP
ACC
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