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參數資料
| 型號： | HTVDS84 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance Microcontroller With Macro Instruction and Voice Synthesizer and Tone Generator(高性能、8位微控制器，帶宏指令、聲話音成器和聲音發生器) |
| 中文描述： | 8位高性能微控制器，帶有宏觀指導和語音合成器和音發生器（高性能，8位微控制器，帶宏指令，聲話音成器和聲音發生器） |
| 文件頁數： | 26/44頁 |
| 文件大小： | 275K |
| 代理商： | HTVDS84 |
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HTVDS84
26
June 7, 2000
Mnemonic
Description
Flag Affected
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of data memory
Set bit of data memory
None
None
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
None
None
None
None
None
None
None
None
None
None
None
None
None
Table Read
TABRDC [m]
TABRDL [m]
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
None
None
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear the Watchdog Timer
Pre-clear the Watchdog Timer
Pre-clear the Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
None
None
None
TO,PD
TO*,PD*
TO*,PD*
None
None
TO,PD
Note: x: 8-bit immediate data
addr: 11-bit program memory address
m: 8-bit data memory address
A: accumulator
i: 0~7 number of bits
*: Flag(s) may be affected by the execution status
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