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參數資料
| 型號： | HTVDS84 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance Microcontroller With Macro Instruction and Voice Synthesizer and Tone Generator(高性能、8位微控制器，帶宏指令、聲話音成器和聲音發生器) |
| 中文描述： | 8位高性能微控制器，帶有宏觀指導和語音合成器和音發生器（高性能，8位微控制器，帶宏指令，聲話音成器和聲音發生器） |
| 文件頁數： | 15/44頁 |
| 文件大?。?/td> | 275K |
| 代理商： | HTVDS84 |
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HTVDS84
15
June 7, 2000
If the main routine and the ISR (Interrupt Ser-
vice Routine) both employ the table read in-
struction, the contents of the TBLH in the main
routine are likely to be changed by the table
read instruction used in the ISR. Errors can oc-
cur. In other words, using the table read in-
struction in the main routine and the ISR
simultaneously should be avoided. However, if
the table read instruction has to be applied in
both the main routine and the ISR, the inter-
ruptissupposedtobedisabledpriortothetable
read instruction. It will not be enabled until the
TBLH has been backed up. All table related in-
structions require two cycles to complete the
operation. These areas may function as normal
program memory depending upon the require-
ments.
Status register
STATUS
This 8-bit register (0AH) consists of a zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD) ,
watchdog time-out flag (TO) and timebase
counter indicator flag (TF). It also records the
status information and controls the operation
sequence.
Except for the TO and PD flags, bits in the sta-
tus register can be altered by instructions simi-
lar to other registers. Any data written into the
status register will not change the TO or PD
flag. Operations related to the status register
may yield different results from those intended.
The TO and PD flags can be altered only by a
Watchdog Timer overflow, chip power-up, clear-
ing the watchdog time or executing the "HALT"
instruction. TF flag is toggle output 1 or 0, and
be transferred by timebase counter overflow .
The Z, OV, AC and C flags generally reflect the
status of the latest operations. The status regis-
ter will not be automatically pushed onto the
stack on entering the interrupt sequence or ex-
ecuting the subroutine call. If the status con-
tents are important and if the subroutine may
corrupt the status register, the programmer
must take precautions and save it properly.
Interrupt
The VDS84 provide a Timebase interrupt in ad-
dition to two sampling rate counter interrupts.
The interrupt control register (INTC; 0BH) in-
cludes interrupt control bits to set the en-
able/disable and the interrupt request flags.
Labels
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a bor-
row does not take place during a subtraction operation; otherwise C is cleared. It
is also affected by a rotate through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or
no borrow from the high nibble into the low nibble in subtraction takes place;
otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by a system power-up or executing the "CLR WDT" instruction. PD
is set by executing the "HALT" instruction.
TO
5
TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" in-
structions. TO is set by a WDT time-out.
6
Undefined, read as "0"
TF
7
TFflagistoggleoutput1or0,andbetransferredbytimebaseCounteroverflow.
Status register
STATUS
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