- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385413 > HY27UA1G1M (Hynix Semiconductor Inc.) 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory PDF資料下載
參數(shù)資料
| 型號： | HY27UA1G1M |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| 中文描述： | 1Gbit的（128Mx8bit / 64Mx16bit）NAND閃存 |
| 文件頁數(shù)： | 22/43頁 |
| 文件大小： | 729K |
| 代理商： | HY27UA1G1M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
Rev 0.5 / Oct. 2004
22
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Automatic Page 0 Read Description.
At powerup, once the supply voltage has reached the threshold level, V
CCth
, all digital outputs revert to their reset
state and the internal NAND device functions (reading, writing, erasing) are enabled.
The device then automatically switches to read mode where, as in any read operation, the device is busy for a time
t
BLBH1
during the data is transferred to the Page Buffer. Once the data transfer is complete the Ready/Busy signal goes
High. The data can then be read out sequentially on the I/O bus by pulsing the Read Enable, RE, signal. Figures 18
and 19 show the power-up waveforms for devices featuring the Automatic Page 0 Read option.
Sequential Row Read Disabled
If the device is delivered with Sequential row read disabled Automatic Read Page 0 at Power-up, only the first page
(Page 0) will be automatically read after the power-on sequence. Refer to Figure 18.
Sequential Row Read Enabled
If the device is delivered with the Automatic Page 0 Read option only (Sequential Row Read Enable), the device will
automatically enter Sequential Row Read mode after the power-up sequence, and start reading Page 0, Page 1, etc.,
until the last memory location is reached, each new page being accessed after a time t
BLBH1
.
The Sequential Row Read operation can be inhibited or interrupted by de-asserting E (set to V
IH
) or by issuing a co-
mand. Refer to Figure 19.
Note: (1). V
CCth
is equal to 2.5V for 3V Power Supply devices.
Figure 18. Sequential Row Read Disabled and Automatic Page 0 Read at power-up
Data
N+1
Data
N
Last
Data
Data
N+2
tBLBH1
Busy
Vccth (1)
Vcc
ALE
CLE
I/O
RE
RB
CE
WE
Data Output
from Address N to Last Byte or Word in Page
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY27UAxxx | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27SS08561M | 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash |
| HY27SS561M | 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash |
| HY27US16561M | 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash |
| HY27US561M | 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY27UAXXX | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27UF081G2A | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash |
| HY27UF081G2A-C | 制造商:SK Hynix Inc 功能描述: |
| HY27UF081G2A-F(P) | 制造商:SK Hynix Inc 功能描述: |
| HY27UF081G2A-S(P) | 制造商:SK Hynix Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。