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參數資料
| 型號： | IRF151CHIP |
| 英文描述： | TRANSISTOR | MOSFET | N-CHANNEL | 60V V(BR)DSS | 40A I(D) | CHIP |
| 中文描述： | 晶體管| MOSFET的| N溝道| 60V的五（巴西）直| 40A條（丁）|芯片 |
| 文件頁數： | 7/11頁 |
| 文件大小： | 661K |
| 代理商： | IRF151CHIP |
www.irf.com
7
Fig 15.
Typical Avalanche Current Vs.Pulsewidth
Fig 16.
Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) = T/ Z
thJC
I
av
=
2 T/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
1
10
100
1000
10000
A
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
EA
TOP Single Pulse
BOTTOM 50% Duty Cycle
ID = 140A
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