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參數資料
型號: IS61QDB21M36-300M3
元件分類: SRAM
英文描述: 1M X 36 DDR SRAM, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, LFBGA-165
文件頁數: 1/27頁
文件大小: 649K
代理商: IS61QDB21M36-300M3
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. H
1/6/2010
36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs
Features
1M x 36 or 2M x 18.
On-chip delay-locked loop (DLL) for wide data
valid window.
Separate read and write ports with concurrent
read and write operations.
Synchronous pipeline read with early write oper-
ation.
Double data rate (DDR) interface for read and
write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K) for address and con-
trol registering at rising edges only.
Two input clocks (C and C) for data output con-
trol.
Two echo clocks (
CQ and CQ) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
HSTL input and output levels.
Registered addresses, write and read controls,
byte writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 36Mb
IS61QDB21Mx36 and IS61QDB22Mx18
are synchronous, high-perfor
mance CMOS static
random access memory
(SRAM) devices. These
These SRAMs have separate I/Os,
eliminating the
need for high-speed bus turnaround.
The rising
edge of K clock initiates the read/write
operation,
and all internal operations are self-timed.
Refer to
the Timing Reference Diagram for Truth
Table
on page
8 for a description of the basic opera-
tions of these SRAMs.
The input address bus operates at double data rate.
The following are registered internally on the rising
edge of the K clock:
Read address
Read enable
Write enable
Byte writes
Data-in for early writes
The following are registered on the rising edge of
the K clock:
Write address
Byte writes
Data-in for second burst addresses
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered half a cycle earlier than the write address. The
first data-in burst is clocked at the same time as the
write command signal, and the second burst is timed
to the following rising edge of the K clock.
During the burst read operation, the data-outs from
the first burst are updated from output registers off
the second rising edge of the C clock (1.5 cycles
later). The data-outs from the second burst are
updated with the third rising edge of the C clock. The
K and K clocks are used to time the data-outs when-
ever the C and C clocks are tied high.
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
.
JANUARY 2010
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相關代理商/技術參數
參數描述
IS61QDB21M36A-250B4I 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin LFBGA
IS61QDB21M36A-250M3L 功能描述:靜態隨機存取存儲器 36Mb 1Mx36 165ball QUAD Sync 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
IS61QDB22M18-250M3 功能描述:靜態隨機存取存儲器 36Mb 2Mbx18 QUAD Sync 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
IS61QDB22M18-250M3L 功能描述:靜態隨機存取存儲器 36Mb 2Mbx18 QUAD Sync 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
IS61QDB22M18A-250M3L 功能描述:靜態隨機存取存儲器 36Mb 2Mx18 165ball QUAD Sync 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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