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參數資料
型號: ISP1130N
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Serial Bus compound hub with integrated keyboard controller
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDIP56
封裝: PLASTIC, SDIP-56
文件頁數: 41/68頁
文件大小: 1786K
代理商: ISP1130N
Philips Semiconductors
ISP1130
USB compound hub with keyboard controller
Objective specification
Rev. 01 — 23 March 2000
41 of 68
9397 750 06895
Philips Electronics N.V. 2000. All rights reserved.
Both timers can be programmed independently to operate in 4 different modes via the
Timer Mode register (TMOD, see
Table 63
). When Timer 0 is in mode 3, Timer 1 can
be programmed to modes 0, 1 or 2 but it cannot set an interrupt request flag or
generate an interrupt.
Each timer consists of two 8-bit registers in the SFR memory space: TLn and THn
(see
Table 66
). The timer registers are incremented every machine cycle of the
80C51 core. Since one machine cycle consists of 6 clock periods, the timer counts at
a rate of
1
6
×
f
MCU_CLOCK
. This corresponds with 2 MHz for the default microcontroller
clock frequency of 12 MHz.
The timers are started and stopped under software control via the SFR TCON (see
Table 67
). Each timer sets its interrupt request flag when the timer register overflows
from all 1’s to all 0’s (normal timer) or to the reload value (auto-reload timer). When a
timer interrupt is generated, the corresponding interrupt request flag is cleared by the
hardware upon entering the interrupt service routine.
Table 63: TMOD register: bit allocation
Timer 1: bits 7 to 4; Timer 0: bits 3 to 0
7
6
GATE
C/T
5
4
3
2
1
0
M1
M0
GATE
C/T
M1
M0
Table 64: TMOD register: bit description
Bit
Symbol
7
GATE
6
C/T
5
M1
4
M0
3
GATE
2
C/T
1
M1
0
M0
Description
Timer 1 counter gate control; must always be 0
Timer 1 counter/timer select; must always be 0
Timer 1 mode selector bit 1; see
Table 63
Timer 1 mode selector bit 0; see
Table 63
Timer 0 counter gate control; must always be 0
Timer 0 counter/timer select; must always be 0
Timer 0 mode selector bit 1; see
Table 63
Timer 0 mode selector bit 0; see
Table 63
Table 65: Timer mode selection
M1, M0
00
01
10
11
Mode
0
1
2
3
Description
13-bit timer
16-bit timer
8-bit auto-reload timer
Timer 0
: TL0 is an 8-bit timer controlled by Timer 0 control bits;
TH0 is an 8-bit timer controlled by Timer 1 control bits
Timer 1
: stopped
Table 66: Timer register addresses
Register
SFR address
TL0
8AH
TH0
8CH
TL1
8BH
TH1
8DH
Description
Timer 0: lower byte
Timer 0: upper byte
Timer 1: lower byte
Timer 1: upper byte
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