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參數資料
| 型號： | ISP1181ADGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數： | 26/70頁 |
| 文件大小： | 341K |
| 代理商： | ISP1181ADGG |
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Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
26 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Remark:
If any change is made to an endpoint configuration which affects the
allocated memory (size, enable/disable), the FIFO memory contents of
all
endpoints
becomes invalid. Therefore, all valid data must be removed from enabled endpoints
before changing the configuration.
Code (Hex): 20 to 2F —
write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F —
read (control OUT, control IN, endpoint 1 to 14)
Transaction —
write/read 1 byte
12.1.2
Write/Read Device Address
This command is used to set the USB assigned address in the Address Register and
enable the USB device. The Address Register bit allocation is shown in
Table 16
.
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the Address Register (accessible by the micro) is not altered by the bus
reset. In response to the standard USB request Set Address the firmware must issue
a Write Device Address command, followed by sending an empty packet to the host.
The
new
device address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 —
write/read Address Register
Transaction —
write/read 1 byte
Table 14:
Bit
Symbol
Reset
Access
Endpoint Configuration Register: bit allocation
7
6
FIFOEN
EPDIR
0
0
R/W
R/W
5
4
3
2
1
0
DBLBUF
0
R/W
FFOISO
0
R/W
FFOSZ[3:0]
0
0
0
0
R/W
R/W
R/W
R/W
Table 15:
Bit
7
Endpoint Configuration Register: bit description
Symbol
Description
FIFOEN
A logic 1 indicates an enabled FIFO with allocated memory.
A logic 0 indicates a disabled FIFO (no bytes allocated).
EPDIR
This bit defines the endpoint direction (0 = OUT, 1 = IN). It also
determines the DMA transfer direction (0 = read, 1 = write).
DBLBUF
A logic 1 indicates that this endpoint has double buffering.
FFOISO
A logic 1 indicates an isochronous endpoint. A logic 0 indicates
a bulk or interrupt endpoint.
FFOSZ[3:0]
Selects the FIFO size according to
Table 5
6
5
4
3 to 0
Table 16:
Bit
Symbol
Reset
Access
Address Register: bit allocation
7
DEVEN
0
R/W
6
5
4
3
2
1
0
DEVADR[6:0]
0
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
| ISP1181BBS | Full-speed Universal Serial Bus peripheral controller |
| ISP1181BDGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181 | Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件) |
| ISP1181DGG | INDUCTOR 4.7NH +-.3NH 0402 SMD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1181ADGG,112 | 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ADGG,118 | 功能描述:USB 接口集成電路 USB 1.1 ADV. DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ADGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181BBS | 制造商:NXP Semiconductors 功能描述:IC CONTROLLER USB PERIPHERAL SMD 制造商:ST-Ericsson 功能描述:CONTROLLER USB PERIPHERAL 48HVQFN |
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