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參數資料
| 型號： | ISP1181ADGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數： | 34/70頁 |
| 文件大小： | 341K |
| 代理商： | ISP1181ADGG |
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Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
34 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Transaction —
read 1 byte
12.2.3
Stall Endpoint/Unstall Endpoint
These commands are used to stall or unstall an endpoint. The commands modify the
content of the Endpoint Status Register (see
Table 31
).
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microcontroller can restall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also reinitialized. This flushes the buffer: if it is an OUT
buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.
Code (Hex): 40 to 4F —
stall (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 80 to 8F —
unstall (control OUT, control IN, endpoint 1 to 14)
Transaction —
none
Table 31:
Bit
Symbol
Endpoint Status Register: bit allocation
7
EPSTAL
EPFULL1
6
5
4
3
2
1
0
EPFULL0
DATA_PID
OVER
WRITE
0
R
SETUPT
CPUBUF
reserved
Reset
Access
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Table 32:
Bit
7
Endpoint Status Register: bit description
Symbol
Description
EPSTAL
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by
an Unstall Endpoint command. The endpoint is automatically
unstalled upon reception of a SETUP token.
EPFULL1
A logic 1 indicates that the secondary endpoint buffer is full.
EPFULL0
A logic 1 indicates that the primary endpoint buffer is full.
DATA_PID
This bit indicates the data PID of the next packet (0 = DATA PID,
1 = DATA1 PID).
OVERWRITE
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing setup actions and wait for a new
Setup packet.
SETUPT
A logic 1 indicates that the buffer contains a Setup packet.
CPUBUF
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
-
reserved
6
5
4
3
2
1
0
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
| ISP1181BBS | Full-speed Universal Serial Bus peripheral controller |
| ISP1181BDGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181 | Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件) |
| ISP1181DGG | INDUCTOR 4.7NH +-.3NH 0402 SMD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1181ADGG,112 | 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ADGG,118 | 功能描述:USB 接口集成電路 USB 1.1 ADV. DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ADGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181BBS | 制造商:NXP Semiconductors 功能描述:IC CONTROLLER USB PERIPHERAL SMD 制造商:ST-Ericsson 功能描述:CONTROLLER USB PERIPHERAL 48HVQFN |
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