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參數資料
| 型號： | ISP1181ADGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數： | 36/70頁 |
| 文件大小： | 341K |
| 代理商： | ISP1181ADGG |
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Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
36 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.2.7
Acknowledge Setup
This command acknowledges to the host that a SETUP packet was received. The
arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands
for the control IN and OUT endpoints. The microcontroller needs to re-enable these
commands by sending an Acknowledge Setup command, see
Section 9.5
.
Code (Hex): F4 —
acknowledge setup
Transaction —
none
12.3 General commands
12.3.1
Read Endpoint Error Code
This command returns the status of the last transaction of the selected endpoint, as
stored in the Error Code Register. Each new transaction overwrites the previous
status information. The bit allocation of the Error Code Register is shown in
Table 35
.
Code (Hex): A0 to AF —
read error code (control OUT, control IN, endpoint 1 to 14)
Transaction —
read 1 byte
3
OVERWRITE
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous setup information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the setup data has finished.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing setup actions and wait for a new
Setup packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
reserved
2
1
SETUPT
CPUBUF
0
-
Table 34:
Bit
Endpoint Status Image Register: bit description
…continued
Symbol
Description
Table 35:
Bit
Symbol
Reset
Access
Error Code Register: bit allocation
7
UNREAD
0
R
6
5
4
3
2
1
0
DATA01
0
R
reserved
0
R
ERROR[3:0]
RTOK
0
R
0
R
0
R
0
R
0
R
Table 36:
Bit
7
Error Code Register: bit description
Symbol
Description
UNREAD
A logic 1 indicates that a new event occurred before the
previous status was read.
DATA01
This bit indicates the PID type of the last successfully received
or transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).
6
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1181B | Full-speed Universal Serial Bus peripheral controller |
| ISP1181BBS | Full-speed Universal Serial Bus peripheral controller |
| ISP1181BDGG | Full-speed Universal Serial Bus peripheral controller |
| ISP1181 | Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件) |
| ISP1181DGG | INDUCTOR 4.7NH +-.3NH 0402 SMD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1181ADGG,112 | 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ADGG,118 | 功能描述:USB 接口集成電路 USB 1.1 ADV. DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ADGGTM | 功能描述:IC USB HOST CTRL FLL-SPD 48TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181BBS | 制造商:NXP Semiconductors 功能描述:IC CONTROLLER USB PERIPHERAL SMD 制造商:ST-Ericsson 功能描述:CONTROLLER USB PERIPHERAL 48HVQFN |
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