欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機控制器
文件頁數: 17/98頁
文件大小: 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
17 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
8.2.1.4
Status register
The Status register is a 2 B read-only register used to record status information on PCI
bus-related events. For bit allocation, see
Table 8
.
2
BM
Bus Master
: Controls the ability of a device to act as a master on the PCI
bus.
0 —
Disables the device from generating PCI accesses. State after
RST# is logic 0.
1 —
Allows the device to behave as a bus master.
Memory Space
: Controls the response of a device to Memory Space
accesses.
0 —
Disables the device response. State after RST# is logic 0.
1 —
Allows the device to respond to memory space accesses.
IO Space
: Controls the response of a device to I/O space accesses.
0 —
Disables the device response. State after RST# is logic 0.
1 —
Allows the device to respond to I/O space accesses.
1
MS
0
IOS
Table 7:
Bit
Command register (address 04h) bit description
…continued
Symbol
Description
Table 8:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Status register (address 06h) bit allocation
15
14
DPE
SSE
0
0
R
R
7
6
FBBC
reserved
0
0
R
R
13
RMA
0
R
5
66MC
0
R
12
RTA
0
R
4
CL
1
R
11
STA
0
R
3
10
DEVSELT[1:0]
0
R
2
reserved
0
R
9
8
MDPE
0
R
0
1
R
1
0
R
0
R
0
R
Table 9:
Bit
15
Status register (address 06h) bit description
Symbol
Description
DPE
Detected Parity Error
: This bit must be set by the device whenever it
detects a parity error, even if the parity error handling is disabled.
SSE
Signaled System Error
: This bit must be set whenever the device asserts
SERR#. Devices that never assert SERR# do not need to implement this
bit.
RMA
Received Master Abort
: This bit must be set by a master device whenever
its transaction, except for Special Cycle, is terminated with Master-Abort. All
master devices must implement this bit.
RTA
Received Target Abort
: This bit must be set by a master device whenever
its transaction is terminated with Target-Abort. All master devices must
implement this bit.
STA
Signaled Target Abort
: This bit must be set by a target device whenever it
terminates a transaction with Target-Abort. Devices that never signal
Target-Abort do not need to implement this bit.
14
13
12
11
相關PDF資料
PDF描述
ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
ISP1581 Universal Serial Bus 2.0 high-speed interface device
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
ISP1582BS Hi-Speed Universal Serial Bus peripheral controller
相關代理商/技術參數
參數描述
ISP1562BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller
ISP1562BE,518 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1562BE,551 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1562BE,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1562BEGA 功能描述:IC USB HOST CTRL HI-SPD 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA,便攜式音頻/視頻,智能電話 接口:I²C,2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤(4x4) 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
主站蜘蛛池模板: 南江县| 井陉县| 玉林市| 正安县| 枣强县| 玉环县| 河南省| 郁南县| 班玛县| 淮滨县| 南召县| 棋牌| 白山市| 二手房| 福海县| 西林县| 友谊县| 普兰县| 绥宁县| 新巴尔虎左旗| 丰顺县| 怀仁县| 吉安市| 砀山县| 镇雄县| 鹿泉市| 高邮市| 柳州市| 玛纳斯县| 绍兴市| 方城县| 秭归县| 岑溪市| 扎囊县| 靖边县| 泾源县| 城口县| 白城市| 布拖县| 新昌县| 和平县|