欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機控制器
文件頁數: 24/98頁
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
24 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
8.2.2.2
FLADJ register
This feature is used to adjust any offset from the clock source that generates the clock that
drives the SOF counter. When a new value is written to these six bits, the length of the
frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is
given in
Table 27
.
[1]
The reserved bits should always be written with the reset value.
8.2.2.3
PORTWAKECAP register
Port Wake Capability (PORTWAKECAP) is a 2 B register used to establish a policy about
which ports are for wake events; see
Table 29
. Bit positions 15 to 1 in the mask
correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit
position indicates that a device connected below the port can be enabled as a wake-up
device and the port may be enabled for disconnect or connect, or overcurrent events as
wake-up events. This is an information only mask register. The bits in this register do not
Table 26:
Legend: * reset value
Bit
7 to 0
SBRN - Serial Bus Release Number register (address 60h) bit description
Symbol
SBRN[7:0]
Access
R
Value
20h*
Description
Serial Bus Specification Release Number
: This
register value is to identify Serial Bus Specification
Rev. 2.0. All other combinations are reserved.
Table 27:
Bit
Symbol
Reset
Access
FLADJ - Frame Length Adjustment register (address 61h) bit allocation
7
6
5
reserved
[1]
0
0
1
R/W
R/W
R/W
4
3
2
1
0
FLADJ[5:0]
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 28:
Bit
7 to 6
5 to 0
FLADJ - Frame Length Adjustment register (address 61h) bit description
Symbol
Description
reserved
-
FLADJ[5:0]
Frame Length Timing Value
: Each decimal value change to this register
corresponds to 16 high-speed bit times. The SOF cycle time—number of
SOF counter clock periods to generate a SOF micro frame length—is
equal to 59488 + value in this field. The default value is decimal 32 (20h),
which gives a SOF cycle time of 60000.
FLADJ value
SOF cycle time
(480 MHz)
59488
59504
59520
:
59984
60000
:
60480
60496
0 (00h)
1 (01h)
2 (02h)
:
31 (1Fh)
32 (20h)
:
62 (3Eh)
63 (3Fh)
相關PDF資料
PDF描述
ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
ISP1581 Universal Serial Bus 2.0 high-speed interface device
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
ISP1582BS Hi-Speed Universal Serial Bus peripheral controller
相關代理商/技術參數
參數描述
ISP1562BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller
ISP1562BE,518 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1562BE,551 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1562BE,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1562BEGA 功能描述:IC USB HOST CTRL HI-SPD 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA,便攜式音頻/視頻,智能電話 接口:I²C,2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤(4x4) 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
主站蜘蛛池模板: 阿尔山市| 桃园市| 清河县| 区。| 瑞金市| 宽甸| 靖江市| 云梦县| 泌阳县| 武鸣县| 奉新县| 桑植县| 桐乡市| 民丰县| 五指山市| 松江区| 左权县| 岑溪市| 县级市| 衢州市| 泾源县| 高清| 滕州市| 比如县| 蕉岭县| 永登县| 灌云县| 卫辉市| 佛山市| 拉萨市| 金秀| 龙海市| 府谷县| 板桥市| 潞城市| 额尔古纳市| 高邑县| 城固县| 敖汉旗| 昌都县| 将乐县|