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參數(shù)資料
型號: ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 43/66頁
文件大小: 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
43 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.4.5
DMA Interrupt Reason register (address: 50h)
This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after
a DMA command has been executed. An interrupt source is cleared by writing logic 1
to the corresponding bit. When reading, AND the value of the bits in this register with
the value of the corresponding bits in the DMA Interrupt Enable register.
The bit allocation is given in
Table 56
.
Table 55:
Bit
7 to 6
DMA Hardware register: bit description
Symbol
Description
ENDIAN[1:0]
These bits determine whether the data bus is swapped between the
internal RAM and the DMA bus. This only applies for GDMA (slave)
mode.
00 —
Normal data representation
16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0]
01 —
Swapped data representation
16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8]
10 —
reserved
11 —
reserved.
Remark:
While operating with the 8-bit data bus, bits ENDIAN[1:0]
should be always set to logic 00.
Selects the polarity of the End-Of-Transfer input; used in GDMA
(slave) mode only.
5
EOT_POL
0 —
EOT is active LOW
1 —
EOT is active HIGH.
reserved; must be set to logic 0.
Selects the DMA acknowledgment polarity.
4
3
-
ACK_POL
0 —
DACK is active LOW
1 —
DACK is active HIGH.
Selects the DMA request polarity.
2
DREQ_POL
0 —
DREQ is active LOW
1 —
DREQ is active HIGH.
Selects the DIOW strobe polarity.
1
WRITE_POL
0 —
DIOW is active LOW
1 —
DIOW is active HIGH.
Selects the DIOR strobe polarity.
0
READ_POL
0 —
DIOR is active LOW
1 —
DIOR is active HIGH.
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