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參數(shù)資料
型號: ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 47/66頁
文件大小: 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
47 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
When a bit is set in the Interrupt register, it indicates that the hardware condition for
an interrupt has occurred. When the Interrupt register content is nonzero, the INT
output will be asserted corresponding to the Interrupt Enable register. On detecting
the interrupt, the external microprocessor must read the Interrupt register and mask it
with the corresponding bits in the Interrupt Enable register to determine the source of
the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition,
various bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF
and bus reset. The DMA controller only has one interrupt bit: the source for a DMA
interrupt is shown in the DMA Interrupt Reason register.
Each interrupt bit can be individually cleared by writing logic 1. The DMA Interrupt bit
can be cleared by writing logic 1 to the related interrupt source bit in the DMA
Interrupt Reason register and writing logic 1 to the DMA bit of the Interrupt register.
Table 65:
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Interrupt register: bit allocation
31
30
29
28
27
26
25
24
reserved
EP7TX
0
0
R/W
17
EP3TX
0
0
R/W
9
reserved
-
-
-
1
SOF
0
0
R/W
EP7RX
0
0
R/W
16
EP3RX
0
0
R/W
8
EP0SETUP
0
0
R/W
0
BRESET
0
unchanged
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
R/W
18
EP4RX
0
0
R/W
10
EP0RX
0
0
R/W
2
PSOF
0
0
R/W
23
22
21
20
19
EP6TX
0
0
R/W
15
EP2TX
0
0
R/W
7
VBUS
0
0
R/W
EP6RX
0
0
R/W
14
EP2RX
0
0
R/W
6
DMA
0
0
R/W
EP5TX
0
0
R/W
13
EP1TX
0
0
R/W
5
HS_STAT
0
0
R/W
EP5RX
0
0
R/W
12
EP1RX
0
0
R/W
4
RESUME
0
0
R/W
EP4TX
0
0
R/W
11
EP0TX
0
0
R/W
3
SUSP
0
0
R/W
Table 66:
Bit
31 to 26
25
24
23
22
21
Interrupt register: bit description
Symbol
Description
-
reserved
EP7TX
Logic 1 indicates the endpoint 7 TX buffer as interrupt source.
EP7RX
Logic 1 indicates the endpoint 7 RX buffer as interrupt source.
EP6TX
Logic 1 indicates the endpoint 6 TX buffer as interrupt source.
EP6RX
Logic 1 indicates the endpoint 6 RX buffer as interrupt source.
EP5TX
Logic 1 indicates the endpoint 5 TX buffer as interrupt source.
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