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參數資料
| 型號： | ISP1761BE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Hi-Speed Universal Serial Bus On-The-Go controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128 |
| 文件頁數： | 25/158頁 |
| 文件大小： | 724K |
| 代理商： | ISP1761BE |
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9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
25 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
The PLL block generates all the main internal clocks required for normal functionality of
various blocks: 30 MHz, 48 MHz and 60 MHz.
No external components are required for the PLL operation.
7.6 Power management
The ISP1761 implements a flexible power management scheme, allowing various power
saving stages.
The usual powering scheme implies programming EHCI registers and the internal
Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed
USB Host Controller with a Hi-Speed USB hub attached.
While the ISP1761 is set in suspend mode, the main internal clocks will be stopped to
ensure minimum power consumption. An internal LazyClock of 100 kHz
±
40 % will
continue running. This allows initiating a resume on one of the following events:
External USB device connect or disconnect
Assertion of the CS_N signal because of any access to the ISP1761
Driving the HC_SUSPEND/WAKEUP_N pin to a LOW logical level will wake up the
Host Controller, and driving the DC_SUSPEND/WAKEUP_N pin to a LOW logical
level will wake up the Peripheral Controller
The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are bidirectional.
These pins should be connected to the GPIO pins of a processor.
The awake state can be verified by reading the LOW level of this pin. If the level is HIGH,
it means that the ISP1761 is in the suspend state.
HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N require pull-up resistors
because in the ISP1761 suspended state these pins become three-state and can be
pulled down, driving them externally by switching the processor’s GPIO lines to the output
mode to generate the ISP1761 wake-up.
The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are three-state
output and also input to the internal wake-up logic.
When in suspend mode, the ISP1761 internal wake-up circuitry will sense the status of
the HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins:
If the pins remain pulled-up, no wake-up will be generated because a HIGH is sensed
by the internal wake-up circuit.
If the pins are externally pulled LOW (for example, by the GPIO lines or just a test by
jumpers), the input to the wake-up circuitry becomes LOW and the wake-up is
internally initiated.
The resume state has a clock-off count timer defined by bits 31 to 16 of the Power Down
Control register. The default value of this timer is 10 ms, meaning that the resume state
will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD
register is set to logic 1, the Host Controller will go into a permanent resume—the normal
functional state. If the RUN/STOP bit is not set during the time determined by the clock-off
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1761BE,518 | 功能描述:USB 接口集成電路 USB HS OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,557 | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE518 | 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB OTG 128LQFP |
| ISP1761BEGE | 功能描述:IC USB CTRL HI-SPEED 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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