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參數資料
| 型號： | ISPLSI 5512VE-125LF388I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數： | 11/25頁 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 256I/O 7.5NS 388FPBGA |
| 標準包裝： | 60 |
| 系列： | ispLSI® 5000VE |
| 可編程類型： | 系統內可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數目： | 16 |
| 宏單元數： | 512 |
| 門數： | 24000 |
| 輸入/輸出數： | 256 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 388-BBGA |
| 供應商設備封裝： | 388-FPBGA（23x23） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI5512VE-125LF388I |
Specifications ispLSI 5512VE
19
Power Consumption
setting operates product terms at their normal full power
consumption. For portions of the logic that can tolerate
longer propagation delays, selecting the slower “low-
power” setting will reduce the power dissipation for these
product terms. Figure 10 shows the relationship between
power and operating frequency.
Power consumption in the ispLSI 5512VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of product terms
used. The product terms have a fuse-selectable speed/
power tradeoff setting. Each group of five product terms
has a single speed/power tradeoff control fuse that acts
on the complete group of five. The fast “high-speed”
300
020
406080
100
120
140
160
fmax (MHz)
I CC
(mA)
Notes: Configuration of 32 16-bit Counters
Typical Current at 3.3V, 25° C
ispLSI 5512VE
High Speed Mode
ispLSI 5512VE
Low Power Mode
0127/5512VE
ICC can be estimated for the ispLSI 5512VE using the following equation:
High Speed Mode: ICC = 30 + (# of PTs * 0.3030) + (# of nets * Fmax * 0.00273)
Low Power Mode: ICC = 30 + (# of PTs * 0.2676) + (# of nets * Fmax * 0.00273)
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Fmax = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of one GLB load
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
400
500
550
450
350
250
600
Figure 10. Typical Device Power Consumption vs fmax
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISPLSI5512VE-125LF388I | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VE-155LB272 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VE-155LB388 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VE-155LF256 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VE-155LF256-125I | 制造商:Lattice Semiconductor Corporation 功能描述:COMPLEX-EEPLD, 512-CELL, 8NS PROP DELAY, 256 Pin, Plastic, BGA |
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