
L64005 MPEG-2 Audio/Video Decoder Technical Manual
3-7
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
eight more bits after eight serial clock data transfer cycles before it stops
accepting data.
Similarly, the L64005 asserts AREQ signal when space is available in the
audio channel buffer. AREQ is deasserted HIGH when the channel is
unable to accept more data. After AREQ is deasserted, the channel can
accept eight more bits after eight serial clock data transfer cycles before
it stops accepting data.
Figure 3.3
Serial Channel
Input Timing
3.3
Memory
Interface
The L64005 reads and writes DRAM memory using the frame store inter-
face, which is used to store frames of video data. During normal opera-
tion, the L64005 directly controls the frame stores. However, the frame
stores can be accessed through the user interface for testing, verication
face,” for more information regarding the frame store interface. The
L64005 Interface also may operate in either Regular or Synchronous
DRAM Modes. See DRAM Interface Select (Group 7, Register 1, bits
4:3) for more information.
3.3.1
Regular DRAM
Signals
BA[8:0]
DRAM Address Bus
Output
This 9-bit output address bus with row/column multiplex
connects directly to DRAM memory, which is used for pic-
ture reconstruction.
BD[63:0]
DRAM Data Bus
Bidirectional
This 64-bit bidirectional data bus is directly connected to
DRAM memory for picture reconstruction.
SERI
SCLKI
VVALID
ERROR
Data Not
Valid
Audio Channel
Error
Video Data
Valid
AVALID