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參數(shù)資料
| 型號： | L64020XQC |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大小： | 370K |
| 代理商： | L64020XQC |
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16
L64020 Single Chip DVD Decoder
SWEn
SDRAM Write Enable
Output
The Memory Interface asserts SWEn for SDRAM write
cycles and holds it deasserted for SDRAM read cycles.
SCLK
SDRAM 81-MHz Clock
Output
This 81 MHz clock signal is derived from the
27 MHz SYSCLK input using the on-chip PLL.
Video Interface
PD[7:0]
Pixel Data Output Bus
Output
The PD[7:0] bus carries the pixel data for the
reconstructed pictures. The pixel data is formatted in
ITU_R BT.601 Y, Cb, Cr chromaticity.
CREF
Chroma Reference
Output
The Video Interface asserts CREF when the Cb
component of Chroma is on PD[7:0] and deasserts it at
all other times.
BLANK
Blank
Output
BLANK is a composite blank output from the L64020
display controller. Its polarity is user-dened.
OSD_ACTIVE
On-Screen Display
Output
The Memory Interface asserts this signal to indicate that
the on-chip OSD pixel on PD[7:0] is nontransparent. This
signal indicates which pixels have mixed OSD.
EXT_OSD[3:0]
Palette Selection Bus
Input
The host controls an external device (such as a character
generator) to write half-bytes across this bus to select
colors from a 16-color look-up table in the L64020 to be
used for external OSD.
HS
Horizontal Sync
Input
HS is the horizontal sync signal from the PAL/NTSC
Encoder. HS is used to reset the horizontal counters in
the display controller. HS should be synchronous to
SYSCLK.
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