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參數資料
| 型號： | L64222 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 13/32頁 |
| 文件大小： | 248K |
| 代理商： | L64222 |
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20
L64222 DVD Audio/Video Decoder
BCLK is derived from one of the ACLK_x inputs under
host control in normal modes and is the CD_BCLK input
in CD Bypass mode.
LRCLK
DAC Left/Right Sample Clock
Output
Used to indicate which samples belong to the left and
right stereo channels. In default mode, LRCLK is
asserted when the right channel sample is on the
ASDATA pin and deasserted when the left channel
sample is on the ASDATA pin. The host can invert the
sense of the clock (HIGH for left channel, LOW for right).
A_ACLK
DAC Clock
Output
This clock is buffered from the selected input ACLK_x
(see the following ACLK_x description). In CD-bypass
mode, this clock comes directly from the CD_ACLK input
pin.
ACLK_32, ACLK_441, ACLK_48
Audio Reference Clocks
Input
Host selectable audio reference clocks from which clocks
for the external DAC, internal DAC Interface, and internal
S/P DIF Interface are derived.
SPDIF_IN
External S/P DIF
Input
This input is directly connected to the SPDIF_OUT pin
when the host selects the S/P DIF Bypass mode.
SPDIF_OUT
S/P DIF Output
Output
IEC60958 formatted output of the L64222’s S/P DIF
Interface in normal modes and SPDIF_IN in S/P DIF
Bypass mode.
VBG
A/D External Bandgap Voltage
Input
A 0.1 uF capacitor is typically connected between this pin
and analog ground when an external bandgap voltage is
used for the Microphone input A/D converter.
VCM
A/D Bypass Capacitor
Input
A 0.1 uF capacitor is typically connected between this pin
and analog ground.
ADAC0/ADAC0n
Audio DAC Channel 0
Output
Analog audio from channel 0 of the optional, internal
audio DAC.
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