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參數(shù)資料
| 型號： | L64222 |
| 廠商： | LSI CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大小： | 248K |
| 代理商： | L64222 |
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16
L64222 DVD Audio/Video Decoder
SCS1n/SBA13 Second SDRAM Chip Select
Output
The L64222 asserts this signal to select the high address
SDRAM chip in systems that have more than one
memory chip. The high address SDRAM chip must have
the same page size as the low address SDRAM chip but
does not have to have the same number of pages.
This pin is also used as SDRAM address line 13 (SBA13)
whena1Mx64 Mbit SDRAM chip is used in the system.
SDQM
SDRAM Control Pin
Output
SDQM is an active HIGH output signal for the SDRAM
data control mask.
SBA[12:0]
SDRAM Address Bus
Output
These signals are the row/column multiplexed address
bus for SDRAM memory. SDRAM is addressed by the
L64222’s microcontroller and the host as if it were RAM.
The Memory Interface converts these addresses to
SDRAM format.
Note:
The SBA12 address line is used only whena1Mx64 Mbit
SDRAM chip is included in the system.
SCASn
SDRAM Column Address Select
Output
The Memory Interface asserts this signal when the
SDRAM column address is on SBA[11:0].
SRASn
SDRAM Row Address Select
Output
The Memory Interface asserts this signal when the
SDRAM row address is on SBA[11:0].
SBD[15:0]
SDRAM Data Bus
Bidirectional
This 16-bit bidirectional data bus is directly connected to
1 M x 16 SDRAM(s) for buffering channel data and
reconstructed pictures.
SWEn
SDRAM Write Enable
Output
The Memory Interface asserts SWEn for SDRAM write
cycles and holds it deasserted for SDRAM read cycles.
SCLK
SDRAM 81 MHz Clock
Output
The 27 MHz SYSCLK input is multiplied by three using
the on-chip PLL to generate the 81 MHz SCLK.
2048
512
×
16
×
bits
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