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參數資料
| 型號： | L64222 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 4/32頁 |
| 文件大小： | 248K |
| 代理商： | L64222 |
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12
L64222 DVD Audio/Video Decoder
the falling edge of READn in a read cycle and on the
falling edge of WRITEn in a write cycle in Intel mode.
Motorola mode uses a separate address strobe, ASn.
ASn
Address Strobe
Input
Active-LOW address strobe input. This signal is used in
Motorola mode to latch the address.
D[7:0]
Host Data Bus
Bidirectional
The host uses the D[7:0] bidirectional data bus to
program the L64222 and access status and bitstream
information during operation. During a read bus cycle,
D[7:0] carries valid information from an internal L64222
register. DTACKn/RDYn or WAITn indicate when the data
on the bus is valid. In write cycles, the data is latched by
the L64222 on the rising edge of DSn/WRITEn.
DSn/WRITEn
Data Strobe/Write Indicator
Input
DSn - Motorola Mode
DSn indicates when the host strobes the data in or out of
the L64222. Read transactions start when DSn, CSn, and
ASn are all LOW. During a write cycle, the L64222
latches the data on the bus on the rising edge of DSn.
WRITEn - Intel Mode
The external host asserts WRITEn to start a write cycle.
READn must be HIGH during a write cycle, and CSn
must be LOW during a write cycle. The address is
registered on the falling edge of WRITEn. The data is
latched by the L64222 on the rising edge of WRITEn.
READ/READn
Read/Write Strobe - Read Indicator
Input
READ - Motorola Mode
The Motorola host asserts READ for a read cycle and
deasserts it for a write cycle. CSn must be asserted to
select the L64222.
READn - Intel Mode
The Intel host asserts READn and holds WRITEn
deasserted to perform a read cycle. The address is
registered on the falling edge of READn. CSn must be
asserted to select the L64222.
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