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參數資料
| 型號： | LC72715PW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數： | 11/26頁 |
| 文件大小： | 167K |
| 代理商： | LC72715PW |
LC72715PW
No.A1650-19/26
Data renewal timing of read register
The timing for rewriting of read register (STAT, BLNO) data is 1ms up to a time point immediately before changing
of INT from H to L.
Read procedure of corrected data
Normally, the status register is first read because of occurrence of interrupt to check the condition of corrected output
data that is output by the interrupt signal, determining whether or not read is necessary. For example, read is not made
till the next interrupt if the error correction result is NG and read is not necessary.
For CCB IF, data read is made at the CCB address, ‘FBh’, and determination is made by means of the status
information added by 16 bits to see if the subsequent data is to be read. When interrupting read, set the CE signal to
“L”.
It is possible to read the register in a manner asynchronous with the interrupt signal. For example, to check the current
receiving state, read the status register to check BLK (data received during block synchronization) and FRM (data
received during frame synchronization). In this case, read data is more close to the current receiving state, when
VH=0 (data subject to horizontal correction only) information is used.
Layer 4 CRC check
To perform layer 4 CRC check, the data group to be checked is transmitted. After transmission, it is determined that
the data group is free from error if the CRC4 pin becomes the H-level output or the status register CRC4 (layer 4 CRC
check result) is ‘1’.
The CRC4 pin or CRC4 flag of status register is either “H” or “1” when all bits of check register in LSI are “0”. To
perform layer 4 CRC check using this function, it is necessary to initialize the CRC check register in LSI before
transmission of one group of one data group. Initialization is made by setting the CRC4_RST (layer 4 CRC check
circuit reset) of control register to ‘1’.
Subsequently, to transmit the layer 4 CRC check data, set CRC4_RST back to 0 to cancel reset.
The generating polynomial of CRC code is as follows: G(X) = X
16 + X12 + X5 + 1
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