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參數資料
| 型號： | LC72715PW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數： | 9/26頁 |
| 文件大小： | 167K |
| 代理商： | LC72715PW |
LC72715PW
No.A1650-17/26
5h <CTL2>: Control register 2 <Write Only>
Register to control the parallel IF setting, vertically-corrected data output method, etc.
ADR
Register Name
Bit
Name
Description
Reset
7
Reserved
Either keep an initial value or set it to 0.
0
6
BLK_RST
Block synchronization circuit reset setting *1
1: Reset ON
0: Reset OFF
0 to be set to cancel reset
0
5
DACK
DACK signal polarity setting (effective for SP=L only)
0: Negative logic for DACK signal polarity
1: Positive logic for DACK signal polarity
0
4
DREQ
DREQ signal polarity setting (effective for SP=L only)
0: Negative logic for DREQ signal polarity
1: Positive logic for DREQ signal polarity
0
3
RDY
RDY signal timing setting (effective for SP=L only)
0: Outputs the RDY signal in the timing 1.
1: Outputs the RDY signal in the timing 2.
0
2
VEC_OUT
Vertically error corrected data output method changeover setting *2
0: No vertically error corrected output if vertical error correction has not been made
1: All data output even when vertical error correction has not been made
0
1
DMA_RD
DMA read control signal selection setting (effective for SP=L only)
0: RD signal used
1: DACK signal used
0
5h
CTL2
0
DMA
DMA transmission function enable setting (effective for SP=L only)
0: DMA transmission not used for reading of corrected data
1: DMA transmission used for reading of corrected data
0
*1 With BLK_RST=1, the block synchronization state and block synchronization protection counter value are cleared.
But this does not affect the functions related to frame synchronization.
*2 With VEC_OUT=1, one frame of data completely free from error. The data similar to the horizontally-corrected data
is output in the timing of output of vertically-corrected data even when vertical correction has not been made.
6h <CRC4>: Layer 4 CRC register <Write Only>
Register for data group writing to check the layer 4 CRC.
Used on with the parallel IF. The dedicated CCB address is to be used for CCB IF.
ADR
Register Name
Bit
Name
Description
Reset
7
CRCDAT7
0
6
CRCDAT6
0
5
CRCDAT5
0
4
CRCDAT4
0
3
CRCDAT3
0
2
CRCDAT2
0
1
CRCDAT1
0
6h
CRC4
0
CRCDAT0
Layer 4 CRC check data setting
By writing value consecutively into this register, the layer 4 CRC check of data
group comprising multiple bytes can be made.
The CRC checked results can be known by checking the CRC4 flag in the status
register or CRC4 pin output.
0
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