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參數資料
| 型號： | LC89057W-VF4 |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數： | 4/61頁 |
| 文件大?。?/td> | 570K |
| 代理商： | LC89057W-VF4 |
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LC89057W-VF4
No.7202-12/61
9. Description of Demodulation Function
The demodulation function is set with RXOPR. An initial value is set to an operating status.
9.1 Clocks
9.1.1 PLL (LPF)
A VCO (Voltage Controlled Oscillator) that can be stopped with PLLOPR is provided on a chip and it is synchronized
with sampling frequencies from 32kHz to 192kHz and with the data with transfer rate from 4MHz to 25MHz.
The PLL clock frequency is selected with PLLSEL. For systems whose input data sampling frequency is 105kHz or
lower, the initial setting of 512fs is recommended. Since the initial output value of the system clock RMCK is set to
1/2 of PLLSEL, the RMCK output is 256fs when a PLL clock frequency is 512fs.
For receptions systems whose sampling frequency is higher than 105kHz, switch the PLL clock frequency to 256fs. If
the same initial output setting is applied, RMCK is 128fs. Then set with PRSEL[1:0] when necessary.
LPF is a pin for PLL loop filter. Connect the following resistance and capacitances by selecting the PLLSEL system
clock. For PLLSEL switching, LPF loop filter parameter is changed. Thus PLLSEL must be set prior to bi-phase data
input.
Clock
R0
C0
C1
512fs
220
0.1
F
0.022
F
256fs
330
0.068
F
0.001
F
Figure 9.1 Loop Filter Configuration
9.1.2 Demodulation Function without Using PLL (TMCK)
The LC89057W-VF4 has a function that processes input bi-phase data using an external clock (external
synchronization function). In normal demodulation processing, the built-in PLL generates a clock that is synchronized
with data and data processing is carried out by the clock. In the LC89057W-VF4, data processing can be also done
by providing a clock synchronized with data instead of the PLL-generated clock via an independent transmission path.
To use the external synchronization function, set the demodulation function without using PLL with EXSYNC, set the
256fs clock with PLLSEL, and set to 1/1 of PLLSEL setting frequency with PRSEL[1:0]. After that input the 256fs
clock synchronized with the input data to TMCK. By this settings, the same operation as PLL demodulation
processing when the 256fs clock is set is performed. In this case, do not connect anything to LPF. Nor is loop filter
necessary. But configured loop filter does not have adverse effect to the operation.
Complete the above settings of external synchronization function prior to bi-phase data input. Pay attention to the
bandwidth of clock transmission path.
A high-precision clock system using an external PLL can be also configured by applying the external synchronization
function.
LPF
R0
C0
C1
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LC89057W-VF4AD-E | 制造商:ON Semiconductor 功能描述: |
| LC89057W-VF4A-E | 功能描述:音頻發送器、接收器、收發器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| LC89057W-VF4A-TBM-E | 制造商:ON Semiconductor 功能描述: 制造商:ON Semiconductor 功能描述:AUDIO I/F RECEIVER |
| LC89058W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:CMOS IC Digital Audio Interface Receiver |
| LC89058WA-E | 功能描述:音頻發送器、接收器、收發器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
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