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| 型號： | LC89057W-VF4 |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數(shù)： | 7/61頁 |
| 文件大?。?/td> | 570K |
| 代理商： | LC89057W-VF4 |
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LC89057W-VF4
No.7202-15/61
9.1.5 Points to notice about switching clock source while PLL is locked
In the state where the PLL is locked, if the XIN source is switched with SELMTD, OCKSEL, and RCKSEL while the
oscillator amplifier is stopped (initial setting), clock continuity is maintained but RERR temporarily outputs an error
(high level) indication. When switched to XIN source, the oscillator amplifier is switched to the operating state at the
same time. Consequently the input fs calculation restarts. At this time, the previous fs calculation value is reset and
compared with the newly calculated fs value. Then those two values are found not identical, that’s why the error is
temporarily issued.
The following settings is required to switch the clock source with SELMTD, OCKSEL, and RCKSEL without
changing the RERR status while PLL is locked.
(1) Set the oscillation amplifier to the continuous operation mode with AMPOPR[1:0].
(2) Set to the mode where fs change is not reflected to the error flag with FSERR.
By one of the above settings, changing of the RERR status can be constrained when the clock source is switched with
SELMTD, OCKSEL, and RCKSEL.
When switching the clock source to XIN from the state where the oscillation amplifier is stopped while the PLL is
locked, the output clock using XIN as the source starts outputting after the oscillation amplifier starts operating.
When the PLL is locked, switching of the clock source from XIN to PLL is performed instantaneously. In either case,
clock continuity is maintained.
9.1.6 Master clock block diagram (TMCK, XIN, XOUT, RMCK, XMCK)
The relationships between the three master clocks, switching, and the frequency division function, are described
below.
The contents in the square brackets [] by the switch and function blocks correspond to the write command names.
Lock/Unlock is automatically switched by PLL locking/unlocking.
Figure 9.2 Master Clock Block Diagram
PLL
1/N
(256fs or 512fs)
Selected Biphase
TMCK (I) 256fs only
XIN (I)
XOUT (O)
RMCK (O)
XMCK (O)
[EXSYNC]
[RCKSEL]
[PLLOPR]
[PLLSEL]
[PRSEL1]
[XRSEL1]
[XINSEL]
[XMSEL1]
[AMPOPR1]
(N=1, 2)
Lock /Unlock
1/N
(N=1, 2)
1/N
(N=1, 2, 4)
1/N
(N=1, 2, 4)
[OCKSEL]
[XMSEL0]
[XRSEL0]
[PRSEL0]
[SELMTD]
[AMPOPR0]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC89057W-VF4AD-E | 制造商:ON Semiconductor 功能描述: |
| LC89057W-VF4A-E | 功能描述:音頻發(fā)送器、接收器、收發(fā)器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| LC89057W-VF4A-TBM-E | 制造商:ON Semiconductor 功能描述: 制造商:ON Semiconductor 功能描述:AUDIO I/F RECEIVER |
| LC89058W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:CMOS IC Digital Audio Interface Receiver |
| LC89058WA-E | 功能描述:音頻發(fā)送器、接收器、收發(fā)器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
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