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參數資料
| 型號： | LM1246AAA/NA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數： | 36/51頁 |
| 文件大小： | 2794K |
| 代理商： | LM1246AAA/NA |
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Pre-Amplifier Interface Registers (Continued)
Bit 5
When this bit is a 0, the full-scale outputs of DACs 1–3 are 0.5V to 4.5V. When it is a 1, the
full-scale level is 0.5V to 2.5V.
Bit 6
When this bit is a 0, the DAC 4 output is independent. When it is a 1, the DAC 4 output is scaled
by 50% and added to the outputs of DACs 1–3.
Bit 7
Reserved and should be set to zero.
Global Video Control:
GLOBALCTRL (0x8439)
Bank
Power
Blank
X
XXXX
BSD
PS
BV
Bit 0
When this bit is a 1, the video outputs are blanked (set to black level). When it is a 0, video is not
blanked.
Bit 1
When this bit is a 1, the analog sections of the preamplifier are shut down for low power
consumption. When it is a 0, the analog sections are enabled.
Bit 2
This bit isa0by default, where Bank Select is enabled. In this mode, Page RAM addressing is in
the standard mode identical to the LM1247. When this bits a 1, the Bank Select is disabled, and
full 512 character address operation is used.
Bits 7–3
Reserved.
Auxiliary Control:
AUXCTRL (0x843A)
Reserved
Horizontal Blank Position
H. Blank
Reserved
H Blnk
X
HBPOS[30]
HBPOS_EN
X
HBD
Bit 0
When this bit is a 0, the horizontal blanking input at pin 24 is gated to the video outputs to provide
horizontal blanking. When it is a 1, the horizontal blanking at the outputs is disabled.
Bit 1
Reserved
Bit 2
When this bit is a 1, the position of the Horizontal Blanking pulse can be programmably varied
relative to the horizontal flyback in number of pixels. When this bit is a 0, which is by default, the
horizontal blanking pulse position will not be programmable.
Bits 6–3
These 4 bits determine the position of the Horizontal Blanking Pulse with respect to the horizontal
flyback in number of pixels.
Bit 7
Reserved
PLL Range:
PLLFREQRNG (0x843E)
Res’d
PLL
Auto Mode
Clamp
Res’d
OSD
V Blank
PLL
Pre-calibration
X
PLL_AUTO
CLMP
X
OOR
VBL
PFR[1:0]
Bit 1–0
These bits must be set to 0 to pre-calibrate the PLL Auto feature.
Bit 2
This is the Vertical Blanking register. When this bit is a 1, vertical blanking is gated to the video
outputs. When set to a 0, the video outputs do not have vertical blanking.
Bit 3
This is the OSD override bit. This should be set to 0 for normal operation. When set to a 1, the
video outputs are disconnected and OSD only is displayed. This is useful for the OSD display of
special conditions such as “No Signal” and “Input Signal Out of Range”, to avoid seeing
unsynchronized video.
Bit 4
Reserved and should be set to zero.
Bit 5
This is the Clamp Polarity bit. When set to a 0, the LM1246 expects a positive going clamp pulse.
When set to a 1, the expected pulse is negative going.
Bit 6
When this bit is set, the PLL Auto Mode will automatically determine the optimum frequency range
of the Phase Locked Loop.
LM1246
www.national.com
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LM1246AAC/NA | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:IC 150MHZ RGB PREAMP 1246 DIP24 |
| LM1246AAC/NA/NOPB | 功能描述:IC PREAMP RGB 150MHZ 24-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| LM1246NA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs |
| LM1247 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs |
| LM1247AAG/NA | 功能描述:IC PREAMP CMOS 150MHZ 24DIP RoHS:否 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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