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參數資料
| 型號： | LTC4260IUH#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 12/30頁 |
| 文件大小： | 295K |
| 描述： | IC HOT SWAP CNTRL I2C 32-QFN |
| 標準包裝： | 73 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 8.5 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 管件 |
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LTC4260
12
4260fc
For more information www.linear.com/LTC4260
The typical LTC4260 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. The device measures card
voltages and currents and records past and present fault
conditions. The system queries each LTC4260 over the
I
2
C periodically and reads the stored information.
The basic LTC4260 application circuit is shown in Figure 1.
External component selection is discussed in detail in the
Design Example section.
Turn-On Sequence
The power supply on a board is controlled by placing
an external N-channel pass transistor (Q1) in the power
path. Note that sense resistor (R
S
) detects current and
capacitor C1 controls the GATE slew rate. Resistor R6
compensates the current control loop while R5 prevents
high frequency oscillations in Q1. Resistors R1, R2 and
R3 provide undervoltage and overvoltage sensing.
Several conditions must be present before the external
switch can be turned on. First the external supply V
DD
must
exceed its undervoltage lockout level. Next the internally
generated supply INTV
CC
must cross its 4.5V undervoltage
threshold. This generates a 60祍 to 120祍 power-on-reset
pulse. During reset the fault registers are cleared and the
applicaTions inForMaTion
control registers are set or cleared as described in the
register section.
After the power-on-reset pulse, the LTC4260 will go
through the following turn-on sequence. First, the UV and
OV pins must indicate that the input power is within the
acceptable range and the BD錚RST pin must be pulled
low. All of these conditions must be satisfied for dura-
tion of 100ms to ensure that any contact bounce during
insertion has ended.
When these initial conditions are satisfied, the ON pin is
checked. If it is high, the external switch turns on. If it
is low, the external switch turns on when the ON pin is
brought high or if a serial bus turn-on command is received.
The switch is turned on by charging up the GATE with a
18礎 current source (Figure 2). The voltage at the GATE
pin rises with a slope equal to 18礎/C1 and the supply
inrush current is set at:
I
INRUSH
=
C
L
C1
"18礎
When the GATE voltage reaches the FET threshold volt-
age, the switch begins to turn on and the SOURCE voltage
follows the GATE voltage as it increases.
16
UV
R3
2.67k
1%
R2
1.74k
1%
5
4 2
1
24
23
18
13
20
14
7
9
10
8
11
R1
49.9k
1%
Z1*
SMBT70A
V
DD
SENSE
LTC4260GN
R6
100k
Q1
FDB3632
R
S
0.010
V
IN
48V
R5
10
C1
6.8nF
C
L
330礔
R7
43.5k
1%
V
OUT
48V
R8
3.57k
1%
R4
100k
C
F
0.1礔
GATE
INTV
CC ADR0 ADR1
NC
ADR2 GND
FB
BD_PRST
TIMER
ADIN
GPIO
4260 F01
SOURCE
OV
ON
SDAI
SDA0
SCL
ALERT
12
19
15
C3
0.1礔
17 6
+
C
T
68nF
*DIODES, INC
BACKPLANE PLUG-IN
CARD
SDA
SCL
ALERT
GND
Figure 1. 5A, 48V Card Resident Application
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