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參數資料
| 型號： | MB91FV130CR-ES |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-Bit RISC Microcontroller |
| 中文描述： | 32-BIT, 33 MHz, RISC MICROCONTROLLER, CPGA299 |
| 封裝： | CERAMIC, PGA-299 |
| 文件頁數： | 15/123頁 |
| 文件大小： | 1362K |
| 代理商： | MB91FV130CR-ES |
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MB91133/MB91F133
15
(Continued)
Pin No.
Pin name
Circuit
type
Function
96
SCK3/PJ2
P
UART3 clock input/output
This function is valid when UART3 clock output specification is per-
mitted. Can be used as a port when UART3 clock output specifi-
cation is prohibited.
95
SIN4/PJ3
P
UART4 data input
This input is always used when UART4 activates input, so output
by ports should be stopped except when carried out intentionally.
Can be used as a port when UART4 data input is not used.
94
SOT4/PJ4
P
UART4 data output
This function is valid when UART4 data output specification is per-
mitted. Can be used as a port when UART4 data output specifica-
tion is prohibited.
93
SCK4/PJ5
P
UART4 clock input/output
This function is valid when UART4 clock output specification is per-
mitted. Can be used as a port when UART4 clock output specifi-
cation is prohibited.
118
119
120
121
122
123
124
125
AN0/PK0
AN1/PK1
AN2/PK2
AN3/PK3
AN4/PK4
AN5/PK5
AN6/PK6
CMP/AN7/PK7
N
A
/
D converter analog input
This is valid when the AICK register specification is analog input.
[ CMP ] level comparator input
Can be used as ports when A/D converter analog input is not used.
126
DREQ0/PL0
F
DMA external transfer request input
This input is always used if selected as the transfer factor for the
DMA controller, so output by ports should be stopped except when
carried out intentionally. Can be used as a port when DMA exter-
nal transfer request input is not used.
127
DACK0/PL1
F
DMA external transfer request reception output
This function is valid when external transfer request reception out-
put specification of the DMA controller is permitted. Can be used
as a port when transfer request reception output specification of
the DMA controller is prohibited.
128
DEOP0/PL2
F
DMA external transfer termination output
This function is valid when external transfer termination output
specification of the DMA controller is permitted.
129
DREQ1/PL3
F
DMA external transfer request input
This input is always used if selected as the transfer factor for the
DMA controller, so output by ports should be stopped except when
carried out intentionally. Can be used as a port when DMA exter-
nal transfer request input is not used.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MB91FV310A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Proprietary 32-bit Microcontroller CMOS |
| MB91FV310APFV-ES | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Proprietary 32-bit Microcontroller CMOS |
| MB91FV319A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91FV319APMT-ES | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91FV319R | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers |
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