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參數(shù)資料
| 型號： | MB91FV130CR-ES |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-Bit RISC Microcontroller |
| 中文描述： | 32-BIT, 33 MHz, RISC MICROCONTROLLER, CPGA299 |
| 封裝： | CERAMIC, PGA-299 |
| 文件頁數(shù)： | 79/123頁 |
| 文件大小： | 1362K |
| 代理商： | MB91FV130CR-ES |
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MB91133/MB91F133
79
14. UART
UART is the general-purpose serial data communications interface to carry out synchronous or asynchronous
communication (start-stop synchronization) with external systems. It has a master/slave-type communications
function (multiprocessor mode: supporting only master side) as well as normal bi-directional communications
function (normal mode).
UART Functions
UART is the general-purpose serial data communications interface that sends and receives serial data to/from
other CPUs and peripheral equipment, and has functions shown in Table 16.1-1.
Table 16.1-1 UART Functions
Note : Start
/
stop bits are not added by UART and only data is transferred.
Table 16.1-2 UART Operations Mode
Data length
: Setting is impossible
*1 : “
+
1” is address
/
data selection bit (A/D) to be used to control communications.
*2 : 1-bit only can be detected for stop bit in case of reception.
Operations mode
Synchronization
method
Stop bit length
Without parity
With parity
0
Normal mode
7-bit or 8-bit
Asynchronous
1-bit or 2-bit
*2
1
Multiprocessor mode
8
+
1*
1
8
Asynchronous
2
Normal mode
Synchronous
N/A
Functions
Data buffer
Full-duplex double buffer
Transfer mode
Clock synchronous (without start-stop bit)
Clock asynchronous (start-stop cycle)
Baud rate
Dedicated baud rate generator is available. Can be selected from 8 types.
External clock input is possible.
Internal clock (Internal clocks that are provided from 16-bit reload timer support-
ing each channel can be used.)
Data length
7-bit (in case of asynchronous normal mode only)
8-bit
Signal method
Non Return to Zero (NRZ) method
Reception error detection
Framing error
Overrun error
Parity error (impossible in case of multiprocessor mode)
Interruption request
Reception interruption (reception completion, reception error detection)
Transmission interruption (transmission completion)
Master/slave-type
communications function
(Multiprocessor mode)
Communication between 1 (master) and n (slaves) is possible
(Only supports master side)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB91F133PBT | 32-Bit RISC Microcontroller |
| MB91133PBT | 32-Bit RISC Microcontroller |
| MB91F133PMT2 | 32-Bit RISC Microcontroller |
| MB91133 | 32-Bit RISC Microcontroller |
| MB91133PMT2 | 32-Bit RISC Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91FV310A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Proprietary 32-bit Microcontroller CMOS |
| MB91FV310APFV-ES | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Proprietary 32-bit Microcontroller CMOS |
| MB91FV319A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91FV319APMT-ES | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91FV319R | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers |
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