欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: MC56F8346
廠商: Motorola, Inc.
英文描述: 56F8346 16-bit Hybrid Controller
中文描述: 56F8346 16位混合控制器
文件頁數: 112/160頁
文件大小: 1415K
代理商: MC56F8346
112
56F8346 Technical Data
Preliminary
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the
peripheral and system (core and memory) clocks. The maximum master clock frequency is
120MHz. Peripheral and system clocks are generated at half the master clock frequency and
therefore at a maximum 60MHz. The SIM provides power modes (Stop, Wait) and clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS,
power modes, and clock enables provide a flexible means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may
be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to
limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be
disabled when unused. Clock enables provide the means to disable individual clocks. Some
peripherals provide further controls to disable unused subfunctions. Refer to the
Part 3, On-Chip
Clock Synthesis (OCCS)
and the
56F8300 Peripheral User Manual
for further details.
6.7 Power-Down Modes Overview
The 56F8346 operates in one of three power-down modes, as shown in
Table 6-3
.
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the
same as the main processor frequency in this architecture. The maximum frequency of operation
is SYS_CLK = 60MHz.
Table 6-3 Clock Operation in Power-Down Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Active
Active
Device is fully functional
Wait
Core and memory
clocks disabled
Active
Peripherals are active and can product interrupts if they
have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
Stop
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關PDF資料
PDF描述
MC56F8346MFV60 56F8346 16-bit Hybrid Controller
MC56F8346VFV60 56F8346 16-bit Hybrid Controller
MC56F8356 56F8356 16-bit Hybrid Controller
MC56F8356VFV60 56F8356 16-bit Hybrid Controller
MC56F8356MFV60 56F8356 16-bit Hybrid Controller
相關代理商/技術參數
參數描述
MC56F8346EVM 制造商:Freescale Semiconductor 功能描述:Tools Development kit Kit Contents:Inst
MC56F8346MFV60 功能描述:數字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8346MFVE 功能描述:數字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8346VFV60 功能描述:數字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8346VFVE 功能描述:數字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
主站蜘蛛池模板: 黄冈市| 汤原县| 阳春市| 水富县| 利津县| 温宿县| 巴南区| 屏东县| 苗栗市| 绿春县| 西平县| 岚皋县| 商洛市| 辽源市| 滕州市| 修文县| 军事| 陇川县| 印江| 故城县| 衡东县| 苍南县| 岐山县| 涟水县| 乌兰浩特市| 孙吴县| 翁源县| 乌兰察布市| 开鲁县| 玉山县| 呈贡县| 淮安市| 朔州市| 大宁县| 涿鹿县| 广东省| 台东市| 高州市| 峨眉山市| 德格县| 临邑县|