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參數資料
| 型號： | MC68C912B32FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 115/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68C912B32FU8 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
115
16 Development Support
Development support involves complex interactions between MC68HC912B32 resources and external
development systems. The following section concerns instruction queue and queue tracking signals,
background debug mode, and instruction tagging.
16.1 Instruction Queue
The CPU12 instruction queue provides at least three bytes of program information to the CPU when
instruction execution begins. The CPU12 always completely finishes executing an instruction before be-
ginning to execute the next instruction. Status signals IPIPE[1:0] provide information about data move-
ment in the queue and indicate when the CPU begins to execute instructions. This makes it possible to
monitor CPU activity on a cycle-by-cycle basis for debugging. Information available on the IPIPE[1:0]
pins is time multiplexed. External circuitry can latch data movement information on rising edges of the
E-clock signal; execution start information can be latched on falling edges.
Table 42
shows the meaning
of data on the pins.
Program information is fetched a few cycles before it is used by the CPU. In order to monitor cycle-by-
cycle CPU activity, it is necessary to externally reconstruct what is happening in the instruction queue.
Internally the MCU only needs to buffer the data from program fetches. For system debug it is necessary
to keep the data and its associated address in the reconstructed instruction queue. The raw signals re-
quired for reconstruction of the queue are ADDR, DATA, R/W, ECLK, and status signals IPIPE[1:0].
The instruction queue consists of two 16-bit queue stages and a holding latch on the input of the first
stage. To advance the queue means to move the word in the first stage to the second stage and move
the word from either the holding latch or the data bus input buffer into the first stage. To start even (or
odd) instruction means to execute the opcode in the high-order (or low-order) byte of the second stage
of the instruction queue.
16.2 Background Debug Mode
Background debug mode (BDM) is used for system development, in-circuit testing, field testing, and
programming. BDM is implemented in on-chip hardware and provides a full set of debug options.
Because BDM control logic does not reside in the CPU, BDM hardware commands can be executed
while the CPU is operating normally. The control logic generally uses CPU dead cycles to execute these
NOTES:
1. Refers to data that was on the bus at the previous E falling edge.
2. Refers to bus cycle starting at this E falling edge.
Table 42 IPIPE Decoding
Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock
1
IPIPE[1:0]
Mnemonic
0:0
—
0:1
LAT
1:0
ALD
1:1
ALL
Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock
2
IPIPE[1:0]
Mnemonic
0:0
—
0:1
INT
1:0
SEV
1:1
SOD
Meaning
No Movement
Latch Data From Bus
Advance Queue and Load From Bus
Advance Queue and Load From Latch
Meaning
No Start
Start Interrupt Sequence
Start Even Instruction
Start Odd Instruction
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