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參數資料
型號: MC68HC05C8A
廠商: Motorola, Inc.
英文描述: Microcontrollers
中文描述: 微控制器
文件頁數: 132/158頁
文件大小: 773K
代理商: MC68HC05C8A
Electrical Specifications
Technical Data
MC68HC05C8A
MC68HCL05C8A
MC68HSC05C8A
Rev. 5.0
132
Electrical Specifications
MOTOROLA
13.11 5.0-V Serial Peripheral Interface Timing
Num
Characteristic
(1)
1. V
DD
= 5.0 Vdc
±
10%; V
SS
= 0 Vdc, T
A
= T
L
to T
H
. Refer to
Figure 13-9
and
Figure 13-10
for timing diagrams.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
f
OP(M)
f
OP(S)
dc
dc
0.5
2.1
f
OP
MHz
1
Cycle time
Master
Slave
t
CYC(M)
t
CYC(S)
2.0
480
t
CYC
ns
2
Enable lead time
Master
Slave
t
Lead(M)
t
Lead(
S
)
(2)
240
ns
3
Enable lag time
Master
Slave
t
L
ag(M)
t
L
ag(S)
(2)
720
ns
4
Clock (SCK) high time
Master
Slave
t
W(SCKH)M
t
W(SCKH)S
340
190
ns
5
Clock (SCK) low time
Master
Slave
t
W(SCKL)M
t
W(SCKL)S
340
190
ns
6
Data setup time (inputs)
Master
Slave
t
SU(M)
t
SU(S)
100
100
ns
7
Data hold time (inputs)
Master
Slave
Slave access time (time-to-data active from high-
impedance state)
Slave disable time (hold time to high-impedance state)
Data valid
Master (before capture edge)
Slave (after enable edge)
(3)
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
Rise time (20% V
DD
to 70% V
DD
, C
L
= 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
Fall time (70% V
DD
to 20% V
DD
, C
L
= 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
H(M)
t
H(S)
100
100
ns
8
t
A
0
120
ns
9
t
DIS
240
ns
10
t
V(M)
t
V(S)
0.25
240
t
CYC(M)
ns
11
t
HO(M)
t
HO(S)
0.25
0
t
CYC(M)
ns
12
t
RM
t
RS
100
2.0
ns
μ
s
13
t
FM
t
FS
100
2.0
ns
μ
s
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