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參數(shù)資料
| 型號(hào)： | MC68HC05X4DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 142/156頁 |
| 文件大小： | 926K |
| 代理商： | MC68HC05X4DW |
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Glossary
MC68HC0X4 Rev 1.0
142
Glossary
MOTOROLA
opcode
— A binary code that instructs the CPU to perform an operation.
open-drain
— An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
operand
— Data on which an operation is performed. Usually a statement consists of an
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
oscillator
— A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
OTPROM
— One-time programmable read-only memory. A nonvolatile type of memory that
cannot be reprogrammed.
overflow
— A quantity that is too large to be contained in one byte or one word.
page zero
— The first 256 bytes of memory (addresses $0000–$00FF).
parity
— An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
PC
— See “program counter (PC).”
peripheral
— A circuit not under direct CPU control.
phase-locked loop (PLL)
— A oscillator circuit in which the frequency of the oscillator is
synchronized to a reference signal.
PLL
— See "phase-locked loop (PLL)."
pointer
— Pointer register. An index register is sometimes called a pointer register because its
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
polarity
— The two opposite logic levels, logic 1 and logic 0, which correspond to two different
voltage levels, V
DD
and V
SS
.
polling
— Periodically reading a status bit to monitor the condition of a peripheral device.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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