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參數資料
型號: MC68HC05X4DW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Microcontroller Unit
中文描述: 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數: 88/156頁
文件大小: 926K
代理商: MC68HC05X4DW
Motorola CAN
MC68HC05X4
88
Motorola CAN
MOTOROLA
MCAN bus timing
register 0 (CBT0)
NOTE:
This register can be accessed only when the RR bit in CCNTRL is set.
SJW1, SJW0 — Synchronization jump width bits
The synchronization jump width defines the maximum number of
system clock (t
SCL
) cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see
Table 1
).
BRP5 – BRP0 — Baud rate prescaler bits
These bits determine the MCAN system clock cycle time (t
SCL
), which
is used to build up the individual bit timing, according to
Table 2
and
the formula in
Figure 11
.
Address:
$0026
Bit 7
6
5
4
3
2
1
Bit 0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Reset:
Undefined
Figure 10. MCAN Bus Timing 0 (CBT0)
Table 1. Synchronization jump width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization jump width
1 t
SCL
cycle
2 t
SCL
cycles
3 t
SCL
cycles
4 t
SCL
cycles
Table 2. Baud rate prescaler
BRP5
0
0
0
0
:
:
1
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler value (P)
1
2
3
4
:
:
64
20-mcan
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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