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參數資料
| 型號： | MCM20014IBB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 1/3” Color VGA Digital Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數： | 16/54頁 |
| 文件大小： | 761K |
| 代理商： | MCM20014IBB |
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MOTOROLA
MCM20014
16
Figure 23. SFCM Frame Waveform with Internal Timing Control Register = 00
h
Figure 24. SFCM Line Waveform with Internal Timing Control Register = 00
h
4.0 MCM20014 Utility Programming Registers
4.1 Register Reference Map
The I
2
C addressing is broken up into groups of 16 and
assigned to a specific digital block. The designated
block is responsible for driving the internal control bus,
when the assigned range of addresses are present on
the internal address bus. The grouping designation and
assigned range are listed in
Table 1
. Each block con-
tains registers which are loaded and read by the digital
and analog blocks to provide configuration control via
the I
2
C serial interface.
Table 2
contains all the I
2
C address assignments. The
table includes a column indicating whether the register
values are shadowed with respect to the sensor inter-
r
Frame Time = 525 row times
Row Time = 780 MCLKs
WOI = 640 Columns x 480 Rows
starting at row 12, column 48
SOF
VCLK
HCLK
BLANK
SYNC
r
r
r
r
r
r
c
c
c
c
c
row 12
row 13
Row Time = vcw
d
+ shr
d
+ shs
d
+ 19
= 749 + 16 + 16 + 19 = 800 MCLK
’
s
Valid Pixel Data
ADC[9:0]
BLANK
HCLK
VCLK
SOF
MCLK
SYNC
T = (16 * sint
d
) + 771 for vcw
d
< 719
T = (16 * sint
d
) + vcw
d
+ 52 for vcw
d
> 718
Ty = 14 + shr
+ shs
d
= 14 + 16 + 16
= 46 MCLK
’
s
Ty
T
Address Range
Block Name
00
h
- 0F
h
Analog Register Interface
10
h
- 1F
h
Global Gain
20
h
- 2F
h
Offset Calibration
30
h
- 3F
h
Post ADC
40
h
- 60
h
Sensor Interface
61
h
- FF
h
Factory Use
Table 1. I
2
C Address Range Assignments
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