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參數資料
| 型號： | MCM20014IBB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 1/3” Color VGA Digital Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數： | 30/54頁 |
| 文件大?。?/td> | 761K |
| 代理商： | MCM20014IBB |
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MOTOROLA
MCM20014
30
5.5 Sensor Interface Block
5.5.1 Sensor Output Control
The sensor output control registers define how the win-
dow of interest is captured and what data is output from
the MCM20014.
The
Capture Mode Control Register; Table 24
, defines
how the data is captured and how the data is to be pro-
vided at the output.
The
sms
bit defines the shutter mode, CFCM or SFCM,
of the device as described in
section 2.1.3
. CFCM is the
default mode.
Setting the
cms
bit will stop the current CFCM output
data stream at the end of the current frame. Unsetting
this bit (
cms
= 0
b
) will resume the output of the frame
stream. The MCM20014 is in CFCM in default. The user
may use this bit to capture data in the CFCM mode
while using the SYNC pin. The SYNC pin triggers a sin-
gle frame of data to be output from the device in the
CFCM mode. Please refer to
Figure 19, on page 14
for
a timing diagram of this mode.
The
frc
bit is used to enable or disable the Frame Rate
Clamp. Unsetting this bit will turn off the frame rate
clamp and the output dark level will begin to drift over
frames. The frame rate clamp is enabled in default
mode.
The
sp
bit is used to define whether SOF is active high
or low. SOF is active high in default.
The
ve
bit is used to determine whether VCLK is output
at the beginning of all the rows including virtual frame
rows or for the WOI rows only. The default is WOI only.
The
vp
bit is used to define whether VCLK is active high
or low. VCLK is active high in default.
The
he
bit is used to determine whether HCLK is output
continously or for the WOI pixels only. The default is
WOI only.
The
hp
bit is used to define whether HCLK is active high
or low. HCLK is active high in default.
6
FUO
FUO
0
b
5
White
Enable
0
b
= Disable White Bad Pixel Replacement
1
b
= Enable White Bad Pixel Replacement
1
b
4
Black
Enable
0
b
= Disable Black Bad Pixel Replacement
1
b
= Enable Black Bad Pixel Replacement
1
b
3
Com-
pander
Slope
0
b
= Invalid when cpb[2:0]
≠
000
b
1
b
= 1:1 input:output
0
b
2 - 0
Com-
pander
Knee
000
b
= linear
001
b
= 15 on the output axis.
010
b
= 31 on the output axis.
011
b
= 47 on the output axis.
100
b
= 63 on the output axis.
101
b
= 79 on the output axis.
110
b
= 95 on the output axis.
111
b
= 127 on the output axis.
000
b
Address
32
h
Post ADC Control
Default
30
h
msb (7)
6
5
4
3
2
1
lsb (0)
cpe
fuo
wpe
bpe
cps
cpb[2]
cpb[1]
cpb[0]
Table 23. Post ADC Control Register
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相關代理商/技術參數 |
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| MCM20014IBMN | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1/3” Color VGA Digital Image Sensor |
| MCM20027 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control |
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| MCM20027IBMN | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control |
| MCM2012B221FBE | 制造商: 功能描述:Chip Common Mode Filter 制造商:undefined 功能描述:Chip Common Mode Filter |
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