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參數資料
| 型號： | MCM20014IBB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 1/3” Color VGA Digital Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數： | 41/54頁 |
| 文件大小： | 761K |
| 代理商： | MCM20014IBB |
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MCM20014
MOTOROLA
41
6.0 I
2
C Serial Interface
The I
2
C is an industry standard which is also compatible
with the Motorola bus (called M-Bus) that is available on
many microprocessor products. The I
2
C contains a se-
rial two-wire half-duplex interface that features bidirec-
tional operation, master or slave modes, and multi-
master environment support. The clock frequency on
the system is governed by the slowest device on the
board. The SDATA and SCLK are the bidirectional data
and clock pins, respectively. These pins are open drain
and will require a pull-up resistor to VDD of 1.5 k
to 10
k
(see
page 48
).
The I
2
C is used to write the required user system data
into the Program Control Registers in the MCM20014.
The I
2
C bus can also read the data in the Program Con-
trol Register for verification or test considerations. The
MCM20014 is a slave only device that supports a max-
imum clock rate (SCLK) of 100 kHz while reading or
writing only one register address per I2C start/stop cy-
cle. The following sections will be limited to the methods
for writing and reading data into the MCM20014 regis-
ter.
For a complete reference to I
2
C, see
“
The I
2
C Bus from
Theory to Practice
”
by Dominique Paret and Carll-
Fenger, published by John Wiley & Sons, ISBN
0471962686.
6.1 MCM20014 I2C Bus Protocol
The MCM20014 uses the I2C bus to write or read one
register byte per start/stop I2C cycle as shown in
Figure
25
and
Figure 26
. These figures will be used to describe
the various parts of the I2C protocol communications as
it applies to the MCM20014.
MCM20014 I2C bus communication is basically com-
posed of following parts: START signal, MCM20014
slave address (0110011
b
) transmission followed by a R/
W bit, an acknowledgment signal from the slave, 8 bit
data transfer followed by another acknowledgment sig-
nal, STOP signal, Repeated START signal, and clock
synchronization.
6.2 START Signal
When the bus is free, i.e. no master device is engaging
the bus (both SCLK and SDATA lines are at logical
“
1
”
),
a master may initiate communication by sending a
START signal. As shown in
Figure 25
, a START signal
is defined as a high-to-low transition of SDATA while
SCLK is high. This signal denotes the beginning of a
new data transfer and wakes up all the slaves on the
bus.
6.3 Slave Address Transmission
The first byte of a data transfer, immediately after the
START signal, is the slave address transmitted by the
master. This is a 7-bit calling address followed by a R/
W bit. The seven-bit address for the MCM20014, start-
ing with the MSB (AD7) is 0110011
b
. The transmitted
calling address on the SDATA line may only be
changed while SCLK is low as shown in
Figure 25
. The
data on the SDATA line is valid on the High to Low sig-
nal transition on the SCLK line. The R/W bit following
the 7-bit tells the slave the desired direction of data
transfer:
Address
53
h
CFCM Virtual Frame Column Width LSB
Default
ED
h
msb (7)
6
5
4
3
2
1
lsb (0)
vcw[7]
vcw[6]
vcw[5]
vcw[4]
vcw[3]
vcw[2]
vcw[1]
vcw[0]
Bit
Number
Function
Description
Reset
State
7 - 0
Virtual Col-
umn Width
In conjunction with the CFCM Virtual Frame Column Width MSB
(
Table 42
) Register, forms the 14-bit Virtual Frame Column Width
vcw[13:0]. WOI is always top-left justified in Virtual Frame.
vcw
d
minimum = wcw
d
+ 11 (CFCM)
vcw
d
minimum = wcw
d
+ 14 (SFCM)
11101101
b
(750 col.)
Table 43. CFCM Virtual Frame Column Width LSB Register
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