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參數(shù)資料
型號: MCM20014IBB
廠商: MOTOROLA INC
元件分類: 模擬信號調(diào)理
英文描述: 1/3” Color VGA Digital Image Sensor
中文描述: SPECIALTY ANALOG CIRCUIT, CQCC48
封裝: CERAMIC, LCC-48
文件頁數(shù): 25/54頁
文件大小: 761K
代理商: MCM20014IBB
MCM20014
MOTOROLA
25
Additional control of the MCM20014 can be had using
the Reset Control Register;
Reset Control Register; Ta-
ble 15
. Setting the
clt
bit of this register will tristate the
sync signals SOF, VLCK, and HCLK.
Setting the
ssr
bit of this register will reset all the non-
user programmable registers to a known reset state.
This is useful in situations when control of the
MCM20014 has been lost due to system interrupts and
the device needs only to be restarted using the earlier
user programmed values.
Setting the
sit
bit allows the user to completely reset the
MCM20014 to the default state via the serial control in-
terface.
For both reset bits,
ssr
and
sit
, the user must return
those bits to 0 to enable continued operation.
5.2 Gain Caliberation Block
The
DPGA Global Gain Register; Table 16
, allows the
user to set a global gain via a 6 bit register this is applied
universally to all the pixel outputs. This enables the user
to account for varying light conditions using a gain
range of 1x to 8x in steps of 0.12x. The default value for
this register results in unity gain.
Address
0E
h
Reset Control
Default
00
h
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
x
x
x
clt
ssr
sit
Bit
Number
Function
Description
Reset
State
7 - 3
Unused
Unused
xxxxx
2
Tristate
0
b
= SOF, VCLK, and HCLK Output Enabled
1
b
= SOF, VCLK, and HCLK Output in Tristate
0
b
1
State
Reset
0
b
= Normal Mode
1
b
= Reset all non-programmable registers to the default state
0
b
0
Soft Reset
0
b
= Normal Mode
1
b
= Reset all registers to default state
0
b
Table 15. Reset Control Register
Address
10
h
Global Gain
Default
00
h
msb (7)
6
5
4
3
2
1
lsb (0)
x
x
gg[5]
gg[4]
gg[3]
gg[2]
gg[1]
gg[0]
Bit
Number
Function
Description
Reset
State
7 - 6
Unused
Unused
xx
5 - 0
Gain
Gain = 1 + (0.12 * gg
d
)
000000
b
Table 16. DPGA Global Gain Register
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