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參數(shù)資料
| 型號： | MCM6929AWJ8R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 4 Bit Fast Static Random Access Memory |
| 中文描述： | 256K X 4 STANDARD SRAM, 8 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 119K |
| 代理商： | MCM6929AWJ8R |
MCM6929A
6
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
6929A–8
6929A–10
6929A–12
6929A–15
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tAVWH
tWLWH,
tWLEH
8
—
10
—
12
—
15
—
ns
3
Address Setup Time
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
8
—
9
—
10
—
12
—
ns
Address Valid to End of Write, G High
7
—
8
—
9
—
10
—
ns
Write Pulse Width
8
—
9
—
10
—
12
—
ns
Write Pulse Width, G High
tWLWH,
tWLEH
7
—
8
—
9
—
10
—
ns
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
4
—
5
—
6
—
7
—
ns
Data Hold Time
0
—
0
—
0
—
0
—
ns
Write Low to Data High–Z
—
4
—
5
—
6
—
7
ns
4,5,6
Write High to Output Active
3
—
3
—
3
—
3
—
ns
4,5,6
Write Recovery Time
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWHDX
tWLQZ
tWHQX
HIGH–Z
HIGH–Z
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
tWLEH
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