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參數資料
| 型號： | MCM6949YJ8R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 4 Bit Static Random Access Memory |
| 中文描述： | 1M X 4 STANDARD SRAM, 8 ns, PDSO32 |
| 封裝： | 0.400 INCH, SOJ-32 |
| 文件頁數： | 8/10頁 |
| 文件大?。?/td> | 122K |
| 代理商： | MCM6949YJ8R |
MCM6949
8
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled; See Notes 1, 2, and 3)
Parameter
Symbol
b l
MCM6949–8
MCM6949–10
MCM6949–12
MCM6949–15
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
tAVAV
tAVWL
tAVWH
tAVWH
tWLWH
tWLEH
8
—
10
—
12
—
15
—
ns
4
Address Setup Time
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
8
—
9
—
10
—
12
—
ns
Address Valid to End of Write (G High)
7
—
8
—
9
—
10
—
ns
Write Pulse Width
8
—
9
—
10
—
12
—
ns
Write Pulse Width (G High)
tWLWH
tWLEH
7
—
8
—
9
—
10
—
ns
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
5
—
5
—
6
—
7
—
ns
Data Hold Time
0
—
0
—
0
—
0
—
ns
Write Low to Data High–Z
0
4
0
5
0
6
0
7
ns
5, 6, 7
Write High to Output Active
3
—
3
—
3
—
3
—
ns
5, 6, 7
Write Recovery Time
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
5. Transition is measured
±
200 mV from steady–state voltage.
6. This parameter is sampled and not 100% tested.
7. At any given voltage and temperature, tWLQZ max < tWHQX min, both for a given device and from device to device.
DATA VALID
HIGH–Z
HIGH–Z
tAVAV
tAVWH
tWHAX
tWHDX
tWHQX
tWLWH
tWLEH
tAVWL
tDVWH
tWLQZ
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
(W Controlled; See Notes 1, 2, and 3)
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