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參數(shù)資料
| 型號(hào)： | MICRF405YML TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 18/46頁(yè) |
| 文件大小： | 649K |
| 描述： | TRANSMITTER ASK/FSK 24-MLF |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 頻率： | 290MHz ~ 980MHz |
| 應(yīng)用： | ISM |
| 調(diào)制或協(xié)議： | ASK，F(xiàn)SK |
| 數(shù)據(jù)傳輸率 - 最大： | 200 kbps |
| 功率 - 輸出： | 10dBm |
| 電流 - 傳輸： | 18mA |
| 數(shù)據(jù)接口： | PCB，表面貼裝 |
| 天線連接器： | PCB，表面貼裝 |
| 電源電壓： | 2.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 24-VFQFN 裸露焊盤(pán)，24-MLF? |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 571 (CN2011-ZH PDF) |
| 其它名稱(chēng)： | 576-1965-6 |
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Micrel
MICRF405
April 2006
18
M9999-041906
(408) 955-1690
Main Modes of Operation
Adr
Data
A6..A0
D7
D6
D5
D4
D3
D2
D1
D0
0000000
Mode1=0 Mode0=1 PA2=1 PA1=1 PA0=1 ClkOut_en=1
Sync_en=1
Load_en=1
There are three main modes of operation and these
are controlled by Mode1-0, see Table 9. In Power
down mode all blocks are shut down, though the
contents of the registers are preserved. In Standby
the crystal oscillator is running and an optional
programmable clock is present on the CLKOUT pin
(Default enabled). This clock can be used as a
micro-controller reference frequency. In TX mode
all blocks are active if not disabled by the user.
Mode1 Mode0
State
Comments
0
0
Power down
Keeps Register
configuration
0
1
1
0
Standby
Crystal Oscillator
running
1
1
Transmit mode
Transmit mode
Table 9. MICRF405 Main Modes.
Power Amplifier
Adr
Data
A6..A0
D7
D6
D5
D4
D3
D2
D1
D0
0000000
Mode1=0
Mode0=1
PA2=1
PA1=1
PA0=1
ClkOut_en=1
Sync_en=1
Load_en=1
0010111
PA_IB3=1
PA_IB2 =0
PA_IB1=0
PA_IB0=1
PAB_IB3=1
PAB_IB2=0
PAB_IB1=0
PAB_IB0=1
The maximum output power is approximately
10dBm. For maximum output power the load seen
by the PA must be resistive and around 150& at
900MHz and 250& at 434MHz and 315Hz. The
output power can be programmed with bits PA[2:0]
to eight different levels if bit PA_LDc_en=1 or seven
levels if PA_LDc_en=0, with approximately 3dB
between each step. If PA_LDc_en=0, the PA is
turned of by setting PA[2:0] to 0. For all other
PA[2:0] combinations, the PA is on and has a
maximum power when PA[2:0]=7. If PA_LDc_en=1
the PA is controlled by the lock detector.
A simple ?LC network can be used to provide the
needed impedance and also to reduce the power of
the harmonics to acceptable levels. Such matching
networks for different frequencies are shown on the
Typical Application Circuit.
The bias setting of the PA and the PA buffer is
controlled by bits PA_IB PA[2:0] and PAB_IB
PA[2:0]. The recommended bit setting, shown in
Table 10, is for the different frequency bands.
Typical values of output power and current
consumption for the different power levels for
different frequencies are shown in Table 11. The
settings used are: Modulation[2:0]=2, ClkOut_en=0,
external loop filter.
Frequency band
(MHz)
PA_IB[2:0]
PAB_IB[2:0]
315
8
8
434
9
8
868
9
9
915
10
9
Table 10. Recommended Settings of PA_IB and PAB_IB vs. Frequency Band.
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