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參數資料
| 型號： | MICRF405YML TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 33/46頁 |
| 文件大小： | 649K |
| 描述： | TRANSMITTER ASK/FSK 24-MLF |
| 標準包裝： | 1 |
| 頻率： | 290MHz ~ 980MHz |
| 應用： | ISM |
| 調制或協議： | ASK，FSK |
| 數據傳輸率 - 最大： | 200 kbps |
| 功率 - 輸出： | 10dBm |
| 電流 - 傳輸： | 18mA |
| 數據接口： | PCB，表面貼裝 |
| 天線連接器： | PCB，表面貼裝 |
| 電源電壓： | 2.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，24-MLF? |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 571 (CN2011-ZH PDF) |
| 其它名稱： | 576-1965-6 |
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Micrel
MICRF405
April 2006
33
M9999-041906
(408) 955-1690
Low Dropout Regulator (LDO) and Low Battery Detector
Adr
Data
A6..A0
D7
D6
D5
D4
D3
D2
D1
D0
0001011 LowBatt_en=1 Freq_Band1=0 Freq_Band0=1 VCO_freq2=0 VCO_freq1=1
VCO_freq0=1 Modulation1=1 Modulation0=0
0001100 LowBatt_level=0
LDO_by=0
LDO_en1=1
LDO_en0=1 MOD_LDc_en=0 PA_FEc_en=0 PA_LDc_en=0
LD_en=1
The MICRF405 has three internal LDOs powering
up different parts of the circuit, as can be seen in the
Block Diagram. The output voltages of the LDOs are
around 2.4V. The LDOs can be turned off (default
setting is on) by setting the LDO_en[1:0]=0.
When LDO_en[1:0]=3, the power supply range is
2.2-3.6 volt. Power must be applied to pin 1 and 11.
A capacitor is needed on each of the LDO output for
stability (pin 3, 9 and 23). In sleep mode, all the
LDOs are turned off. The interface and control
blocks run on unregulated power, meaning that the
register content will be kept and that the
programming can also be done in this mode.
An option, where the LDOs are bypassed, is
enabled by setting the LDO_by bit, and when
activated, the transmitter can operate at 2.2V-2.5V.
Since the LDO drop is decreased, the output power
is slightly higher. However, in this mode it is of vital
importance that the input power is below 2.5V as the
pass devices in the LDOs are fully on and not
regulated. It is recommended that this option is used
in combination with the low battery detector.
When LDO_en[1:0]=0, the power supply range is
2.2-2.5 volt. Power must be applied to pin 1, 3, 9, 11
and 23. Capacitors are now only needed for normal
noise decoupling. Alternatively, connect power to
pins 1 and 11 only, and set LDO[1:0]=3 and
LDO_by=0.
The LDOs are controlled with 2 bits, enabling the
option of running the complete circuit on the RF LDO
alone (LDO_en[1:0]=1), or on the RF LDO and
analog LDO (LDO_en[1:0]=2). Doing so, regulated
power on the RFVDD pin must be externally routed
to the AVDD and DVDD pin in the first case and,
and from the RFVDD to the DVDD pin in the second
case. These modes will save one or two of the
external capacitors used for stabilizing the LDOs,
but might influence the phase noise and spurious
performance. Recommended use is therefore,
LDO_en[1:0]=3 or 0.
The low battery detector circuit is turned on when
the LowBatt_en bit is set. It will monitor the voltage
of the input power, pin 11, in standby and TX
modes. If LDO_by=0, it will set the LowBatt interrupt
if the voltages falls below 2.1V for LowBatt_level=1
and 2.0V for LowBatt_level=0. If LDO_by=1, it sets
the interrupt when the voltages is below 1.9V/1.8V
for LowBatt_level=1/0.
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