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參數資料
| 型號： | MPC603E7TED |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微處理器的PowerPC 603e |
| 文件頁數： | 3/36頁 |
| 文件大小： | 551K |
| 代理商： | MPC603E7TED |
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PID7t-603e Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
3
Features
supports block address translation through the use of two independent instruction and data block address
translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously
with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,
if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows
multiple masters to compete for system resources through a central external arbiter. The 603e provides a
three-state coherency protocol that supports the exclusive, modiTed, and invalid cache states. This protocol
is a compatible subset of the MESI (modiTed/exclusive/shared/invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The 603e supports single-beat and burst data transfers
for memory accesses, and supports memory-mapped I/O.
The 603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface compatibility
with TTL devices. The PID7t-603e is offered in both PBGA and CBGA packages. The CBGA package
supports speed bins of 200 MHz, 266 MHz, and 300 MHz. The PBGA package is a pin-compatible drop in
replacement for the CBGA; however this package only supports speeds up to 200 MHz.
1.2 Features
This section summarizes features of the 603es implementation of the PowerPC architecture. Major features
of the 603e are as follows:
￥
High-performance, superscalar microprocessor
As many as three instructions issued and retired per clock
As many as Tve instructions in execution per clock
Single-cycle execution for most instructions
Pipelined FPU for all single-precision and most double-precision operations
￥
Five independent execution units and two register Tles
BPU featuring static branch prediction
A 32-bit IU
Fully IEEE 754-compliant FPU for both single- and double-precision operations
LSU for data transfer between data cache and GPRs and FPRs
SRU that executes condition register (CR), special-purpose register (SPR) instructions, and
integer add/compare instructions
Thirty-two GPRs for integer operands
Thirty-two FPRs for single- or double-precision operands
￥
High instruction and data throughput
Zero-cycle branch capability (branch folding)
Programmable static branch prediction on unresolved conditional branches
Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
A six-entry instruction queue that provides lookahead capability
Independent pipelines with feed-forwarding that reduces data dependencies in hardware
16-Kbyte data cachefour-way set-associative, physically addressed; LRU replacement
algorithm
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Freescale Semiconductor, Inc.
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