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參數資料
| 型號： | MPC603E7TED |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微處理器的PowerPC 603e |
| 文件頁數： | 8/36頁 |
| 文件大小： | 551K |
| 代理商： | MPC603E7TED |
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8
PID7t-603e Hardware Specifications
Electrical and Thermal Characteristics
1.4.2.1 Clock AC SpeciTcations
Table 7 provides the clock AC timing speciTcations as deTned in Figure 1. After fabrication, parts are sorted
by maximum processor core frequency as shown in Section 1.4.2.1, òClock AC SpeciTcations,ó and tested
for conformance to the AC speciTcations for that frequency. Parts are sold by maximum processor core
frequency; see Section 1.9, òOrdering Information.ó
Table 7. Clock AC Timing Specifications
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc
,
0
￡
Tj
￡
105 °C
Num
Characteristic
200 MHz
PBGA
200 MHz
CBGA
266 MHz
CBGA
300 MHz
CBGA
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Processor
frequency
100
200
80
200
150
266
180
300
MHz
1,6
VCO
frequency
300
400
300
400
300
532
360
600
MHz
1
SYSCLK
frequency
25
66.67
25
66.67
25
75
33.3
75
MHz
1
1
SYSCLK
cycle time
13.3
40
13.3
40
13.3
40
13.3
30
ns
2,3
SYSCLK rise
and fall time
—
2.0
—
2.0
—
2.0
—
2.0
ns
2
4
SYSCLK duty
cycle measured at
1.4 V
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
—
±150
—
±150
—
±150
—
±150
ps
4
PID7t internal
PLL-relock time
—
100
—
100
—
100
—
100
m
s
3,5
Notes
:
1.
Caution
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description
in Section 1.8, “System Design Information,” for valid PLL_CFG[0–3] settings.
: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term
combined) must be under ±150 ps to guarantee the input/output timing of Section 1.4.2.2, “Input AC
Specifications,” and Section 1.4.2.3, “Output AC Specifications.”
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during
the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time (100
m
s) during the power-on reset sequence.
6. Operation below 150 MHz is supported only by PLL_CFG[0–3] = 0b0101. Refer to Section 1.8.1, “PLL
Configuration” for additional information.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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