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參數(shù)資料
| 型號： | MPC603E7TED |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微處理器的PowerPC 603e |
| 文件頁數(shù)： | 4/36頁 |
| 文件大小： | 551K |
| 代理商： | MPC603E7TED |
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4
PID7t-603e Hardware Specifications
General Parameters
16-Kbyte instruction cachefour-way set-associative, physically addressed; LRU replacement
algorithm
Cache write-back or write-through operation programmable on a per page or per block basis
BPU that performs CR lookahead operations
Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
A 64-entry, two-way set-associative ITLB
A 64-entry, two-way set-associative DTLB
Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
Software table search operations and updates supported through fast trap mechanism
52-bit virtual address; 32-bit physical address
￥
Facilities for enhanced system performance
A 32- or 64-bit split-transaction external data bus with burst transfers
Support for one-level address pipelining and out-of-order bus transactions
￥
Integrated power management
Low-power 2.5/3.3-volt design
Internal processor/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1,
5.5:1, and 6:1 ratios
Three power saving modes: doze, nap, and sleep
Automatic dynamic power reduction when internal functional units are idle
￥
In-system testability and debugging features through JTAG boundary-scan capability
1.3 General Parameters
The following list provides a summary of the general parameters of the PID7t-603e:
Technology
0.29
μ
m CMOS, Tve-layer metal
Die size
5.65 mm x 7.7 mm (44 mm
2
)
Transistor count
2.6 million
Logic design
Fully-static
Package
255 ceramic ball grid array (CBGA)
or 225 thin map plastic ball grid array (PBGA)
Core power supply
2.5 ± 5% V dc
I/O power supply
3.3 ± 5% V dc
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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