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參數資料
| 型號： | MPC99J93 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver |
| 中文描述： | 智能動態時鐘開關（IDC機房）PLL時鐘驅動器 |
| 文件頁數： | 5/8頁 |
| 文件大小： | 265K |
| 代理商： | MPC99J93 |
MPC99J93
MOTOROLA TIMING SOLUTIONS
5
Table 5. AC Characteristics
(V
CC
= 3.3V
±
5%, T
A
= --40
°
C to +85
°
C)
a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
f
ref
f
VCO
f
MAX
Input Reference Frequency
VCO Frequency Range
b
÷
4 feedback
50
90
MHz
PLL locked
÷
4 feedback
200
360
MHz
Output Frequency
QA[1:0]
QB[2:0]
50
100
90
180
MHz
MHz
PLL locked
f
refDC
t
(
)
Reference Input Duty Cycle
25
75
%
Propagation Delay
SPO, static phase offset
c
CLK0, CLK1 to any Q
-0.15
0.9
+0.17
1.8
ns
ns
PLL_EN=1
PLL_EN=0
V
PP
V
CMR
t
sk(O)
Differential input voltage
d
Differential input crosspoint voltage
e
(peak-to-peak)
0.25
1.3
V
V
CC
-1.7
V
CC
-0.3
50
80
V
Output-to-output Skew
within QA[2:0] or QB[1:0]
within device
ps
ps
per/cycle
Rate of change of period
QA[1:0]
f
QB[2:0]
f
QA[1:0]
g
QB[2:0]
g
20
10
200
100
50
25
400
200
ps
ps
ps
ps
DC
Output Duty Cycle
45
50
55
%
t
JIT(CC)
t
LOCK
t
r
, t
f
a. AC characteristics apply for parallel output termination of 50
to V
CC - 2V
.
b. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): f
ref
= f
VCO
÷
FB.
c. CLK0, CLK1 to Ext_FB.
d. V
PP
is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew. Ap-
plicable to CLK0, CLK1 and Ext_FB.
e. V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
(AC)
range and the input swing lies within the V
PP
(AC) specification. Violation of V
CMR
(AC) or V
PP
(AC) impacts the SPO, device and part-to-
part skew. Applicable to CLK0, CLK1 and Ext_FB.
f.
Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change
per cycle is averaged over the clock switch excursion.
g. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (
±
180
_
). Delta period change per
cycle is averaged over the clock switch excursion.
Cycle-to-Cycle Jitter
RMS (1
σ
)
25
ps
Maximum PLL Lock Time
10
ms
Output Rise/Fall Time
0.05
0.70
ns
20% to 80%
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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